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[PATCH v14 7/8] [RISCV_PM] Implement address masking functions required
From: |
Alexey Baturo |
Subject: |
[PATCH v14 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension |
Date: |
Sun, 17 Oct 2021 20:27:27 +0300 |
From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 20 ++++++++++++++++++++
target/riscv/translate.c | 39 +++++++++++++++++++++++++++++++++++++--
2 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index acb4ce9d23..0ae12b9e61 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -407,6 +407,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
+/* If PointerMasking should be applied */
+FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
@@ -467,6 +469,24 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
*env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
get_field(env->mstatus_hs, MSTATUS_FS));
}
+ if (riscv_has_ext(env, RVJ)) {
+ int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
+ bool pm_enabled = false;
+ switch (priv) {
+ case PRV_U:
+ pm_enabled = env->mmte & U_PM_ENABLE;
+ break;
+ case PRV_S:
+ pm_enabled = env->mmte & S_PM_ENABLE;
+ break;
+ case PRV_M:
+ pm_enabled = env->mmte & M_PM_ENABLE;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9e176b8137..e1a5725395 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -36,6 +36,9 @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
+/* globals for PM CSRs */
+static TCGv pm_mask[4];
+static TCGv pm_base[4];
#include "exec/gen-icount.h"
@@ -82,6 +85,10 @@ typedef struct DisasContext {
TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
+ /* PointerMasking extension */
+ bool pm_enabled;
+ TCGv pm_mask;
+ TCGv pm_base;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -248,11 +255,20 @@ static void gen_jal(DisasContext *ctx, int rd,
target_ulong imm)
}
/*
- * Temp stub: generates address adjustment for PointerMasking
+ * Generates address adjustment for PointerMasking
*/
static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
{
- return src;
+ TCGv temp;
+ if (!s->pm_enabled) {
+ /* Load unmodified address */
+ return src;
+ } else {
+ temp = temp_new(s);
+ tcg_gen_andc_tl(temp, src, s->pm_mask);
+ tcg_gen_or_tl(temp, temp, s->pm_base);
+ return temp;
+ }
}
#ifndef CONFIG_USER_ONLY
@@ -536,6 +552,10 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->w = false;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
+ ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+ int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
+ ctx->pm_mask = pm_mask[priv];
+ ctx->pm_base = pm_base[priv];
ctx->zero = tcg_constant_tl(0);
}
@@ -649,4 +669,19 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
+#ifndef CONFIG_USER_ONLY
+ /* Assign PM CSRs to tcg globals */
+ pm_mask[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
+ pm_base[PRV_U] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
+ pm_mask[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
+ pm_base[PRV_S] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
+ pm_mask[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
+ pm_base[PRV_M] =
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
+#endif
}
--
2.30.2
- [PATCH v14 0/8] RISC-V Pointer Masking implementation, Alexey Baturo, 2021/10/17
- [PATCH v14 1/8] [RISCV_PM] Add J-extension into RISC-V, Alexey Baturo, 2021/10/17
- [PATCH v14 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension, Alexey Baturo, 2021/10/17
- [PATCH v14 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode, Alexey Baturo, 2021/10/17
- [PATCH v14 4/8] [RISCV_PM] Add J extension state description, Alexey Baturo, 2021/10/17
- [PATCH v14 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2021/10/17
- [PATCH v14 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2021/10/17
- [PATCH v14 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension,
Alexey Baturo <=
- [PATCH v14 8/8] [RISCV_PM] Allow experimental J-ext to be turned on, Alexey Baturo, 2021/10/17