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Re: [PATCH v3 5/6] target/riscv: zfh: half-precision floating-point clas
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify |
Date: |
Mon, 18 Oct 2021 10:01:26 +1000 |
On Sat, Oct 16, 2021 at 7:11 PM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/fpu_helper.c | 6 ++++++
> target/riscv/helper.h | 1 +
> target/riscv/insn32.decode | 1 +
> target/riscv/insn_trans/trans_rvzfh.c.inc | 12 ++++++++++++
> 4 files changed, 20 insertions(+)
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index ec2009ee65b..388e23ca670 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -482,6 +482,12 @@ target_ulong helper_feq_h(CPURISCVState *env, uint64_t
> rs1, uint64_t rs2)
> return float16_eq_quiet(frs1, frs2, &env->fp_status);
> }
>
> +target_ulong helper_fclass_h(uint64_t rs1)
> +{
> + float16 frs1 = check_nanbox_h(rs1);
> + return fclass_h(frs1);
> +}
> +
> target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1)
> {
> float16 frs1 = check_nanbox_h(rs1);
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 9c89521d4ad..d25cf725c57 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -89,6 +89,7 @@ DEF_HELPER_FLAGS_2(fcvt_h_w, TCG_CALL_NO_RWG, i64, env, tl)
> DEF_HELPER_FLAGS_2(fcvt_h_wu, TCG_CALL_NO_RWG, i64, env, tl)
> DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl)
> DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl)
> +DEF_HELPER_FLAGS_1(fclass_h, TCG_CALL_NO_RWG_SE, tl, i64)
>
> /* Special functions */
> DEF_HELPER_2(csrr, tl, env, int)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 3906c9fb201..6c4cde216bc 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -754,6 +754,7 @@ fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
> feq_h 1010010 ..... ..... 010 ..... 1010011 @r
> flt_h 1010010 ..... ..... 001 ..... 1010011 @r
> fle_h 1010010 ..... ..... 000 ..... 1010011 @r
> +fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
> fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
> fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
> fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc
> b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index 8d0959a6671..0549e25fb45 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -372,6 +372,18 @@ static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a)
> return true;
> }
>
> +static bool trans_fclass_h(DisasContext *ctx, arg_fclass_h *a)
> +{
> + REQUIRE_FPU;
> + REQUIRE_ZFH(ctx);
> +
> + TCGv dest = dest_gpr(ctx, a->rd);
> +
> + gen_helper_fclass_h(dest, cpu_fpr[a->rs1]);
> + gen_set_gpr(ctx, a->rd, dest);
> + return true;
> +}
> +
> static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a)
> {
> REQUIRE_FPU;
> --
> 2.25.1
>
>
- [PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1, frank . chang, 2021/10/16
- [PATCH v3 2/6] target/riscv: zfh: half-precision computational, frank . chang, 2021/10/16
- [PATCH v3 4/6] target/riscv: zfh: half-precision floating-point compare, frank . chang, 2021/10/16
- [PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify, frank . chang, 2021/10/16
- Re: [PATCH v3 5/6] target/riscv: zfh: half-precision floating-point classify,
Alistair Francis <=
- [PATCH v3 3/6] target/riscv: zfh: half-precision convert and move, frank . chang, 2021/10/16
- [PATCH v3 6/6] target/riscv: zfh: implement zfhmin extension, frank . chang, 2021/10/16
- Re: [PATCH v3 0/6] target/riscv: support Zfh, Zfhmin extension v0.1, Richard Henderson, 2021/10/16