Re: [PATCH v7 16/21] target/loongarch: Add disassembler

[Song Gao]

Hi, all.

On 10/19/2021 02:57 AM, Philippe Mathieu-Daudé wrote:
> On 10/18/21 20:33, Richard Henderson wrote:
>> On 10/18/21 11:18 AM, WANG Xuerui wrote:
>>> On 10/19/21 01:29, Richard Henderson wrote:
>>>> On 10/18/21 8:38 AM, WANG Xuerui wrote:
>>>>>
>>>>> For now any implementation would suffice, and I already saw one or
>>>>> two bugs in the output during my TCG host work, but it surely would
>>>>> be nice to switch to generated decoder in the future. The
>>>>> loongarch-opcodes tables could be extended to support peculiarities
>>>>> as exhibited in the v1.00 ISA manual and binutils implementation,
>>>>> via additional attributes, and I'm open to such contributions.
>>>>
>>>> Perhaps it would be easiest to re-use the decodetree description?
>>>> See e.g. target/openrisc/disas.c.
>>>>
>>> Indeed; I didn't thought of disassemblers in target/ instead of
>>> disas/. That would be the most elegant way forward!
>>
>>
>> The one quirk will be that so far using decodetree for disas is limited
>> to the target, whereas you'll want this for host as well.  It shouldn't
>> be a big deal, just a small matter of the correct build rules.
> 
> Oh, good to know. OTOH I expect very few developers to look at
> host disas.
> 

Sorry to reply too late, I asked for leave yesterday.

This patch refers to disas/riscv.c. 

I didn't notice target/openrisc/disas.c before.  Thanks for Richard' advice.


Thanks
Song Gao