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Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructi
From: |
Richard Henderson |
Subject: |
Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions |
Date: |
Wed, 20 Oct 2021 10:47:36 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 |
On 10/19/21 2:48 AM, Frédéric Pétrot wrote:
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e8f08f921e..71982f6284 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -429,6 +429,17 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
+ if (get_xl_max(ctx) == MXL_RV128) {
+ if (get_ol(ctx) == MXL_RV128) {
+ uint64_t immh = -(a->imm < 0);
+ src1 = get_gprh(ctx, a->rs1);
+ dest = dest_gprh(ctx, a->rd);
+
+ func(dest, src1, immh);
+ }
+ gen_set_gprh(ctx, a->rd, dest);
+ }
If ol < RV128, you're storing the low dest into the gprh, which is wrong. It should be
the sign-extension of the low part. But that should happen for all writes.
Earlier, I suggested gen_set_gpr128 instead of gen_set_gprh.
I think this should be written
if (get_xl(ctx) == MXL_RV128) {
TCGv src1h = get_gprh(ctx, a->rs1);
TCGv desth = dest_gprh(ctx, a->rd);
func(dest, src1h, -(a->imm < 0));
gen_set_gpr128(ctx, a->rd, dest, desth);
} else {
gen_set_gpr(ctx, a->rd, dest);
}
Where gen_set_gpr will handle the sign-extension to 128-bits.
@@ -443,6 +454,17 @@ static bool gen_logic(DisasContext *ctx, arg_r *a,
DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
+ if (get_xl_max(ctx) == MXL_RV128) {
+ if (get_ol(ctx) == MXL_RV128) {
+ dest = dest_gprh(ctx, a->rd);
+ src1 = get_gprh(ctx, a->rs1);
+ src2 = get_gprh(ctx, a->rs2);
+
+ func(dest, src1, src2);
+ }
+ gen_set_gprh(ctx, a->rd, dest);
+ }
Similarly.
r~
- Re: [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, (continued)
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/19
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19
- [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/19
- [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/19
- [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/19
- Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions,
Richard Henderson <=
- [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 15/21] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/19