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[PATCH 07/33] target/ppc: Implement cntlzdm
From: |
matheus . ferst |
Subject: |
[PATCH 07/33] target/ppc: Implement cntlzdm |
Date: |
Thu, 21 Oct 2021 16:45:21 -0300 |
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
cntlzdm: Count Leading Zeros Doubleword Under Bit Mask
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 1 +
target/ppc/int_helper.c | 18 ++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
4 files changed, 32 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6fa3e15fe9..ee7c82fb60 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(CNTLZDM, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9cb9fc00b8..221cb00dd6 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -203,6 +203,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
+CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b3d302390a..dcef356034 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -386,6 +386,24 @@ uint64_t helper_cfuged(uint64_t src, uint64_t mask)
return left | (right >> n);
}
+uint64_t helper_CNTLZDM(uint64_t src, uint64_t mask)
+{
+ uint64_t sel_bit, count = 0;
+
+ while (mask != 0) {
+ sel_bit = 0x8000000000000000ULL >> clz64(mask);
+
+ if (src & sel_bit) {
+ break;
+ }
+
+ count++;
+ mask &= ~sel_bit;
+ }
+
+ return count;
+}
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 0a6b3d61d1..814fef2782 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -415,3 +415,15 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_CNTLZDM(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
- [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c, (continued)
- [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c, matheus . ferst, 2021/10/21
- [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree, matheus . ferst, 2021/10/21
- [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions, matheus . ferst, 2021/10/21
- [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree, matheus . ferst, 2021/10/21
- [PATCH 06/33] target/ppc: Implement PLQ and PSTQ, matheus . ferst, 2021/10/21
- [PATCH 07/33] target/ppc: Implement cntlzdm,
matheus . ferst <=
- [PATCH 08/33] target/ppc: Implement cnttzdm, matheus . ferst, 2021/10/21
- [PATCH 09/33] target/ppc: Implement pdepd instruction, matheus . ferst, 2021/10/21
- [PATCH 10/33] target/ppc: Implement pextd instruction, matheus . ferst, 2021/10/21
- [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc, matheus . ferst, 2021/10/21