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[PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vm
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From: |
Alistair Francis |
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Subject: |
[PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v |
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Date: |
Fri, 22 Oct 2021 23:37:40 +1000 |
From: Frank Chang <frank.chang@sifive.com>
oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211007081803.1705656-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 081a5ca34d..45be491ed4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1619,7 +1619,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ cpu_env, s->vlen / 8, s->vlen / 8, data,
+ fns[s->sew]);
gen_set_label(over);
}
return true;
--
2.31.1
- [PULL 00/33] riscv-to-apply queue, Alistair Francis, 2021/10/22
- [PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v,
Alistair Francis <=
- [PULL 02/33] target/riscv: line up all of the registers in the info register dump, Alistair Francis, 2021/10/22
- [PULL 03/33] target/riscv: Fix orc.b implementation, Alistair Francis, 2021/10/22
- [PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory, Alistair Francis, 2021/10/22
- [PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, Alistair Francis, 2021/10/22
- [PULL 06/33] target/riscv: Remove some unused macros, Alistair Francis, 2021/10/22
- [PULL 07/33] target/riscv: Organise the CPU properties, Alistair Francis, 2021/10/22
- [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line, Alistair Francis, 2021/10/22
- [PULL 09/33] target/riscv: Create RISCVMXL enumeration, Alistair Francis, 2021/10/22
- [PULL 10/33] target/riscv: Split misa.mxl and misa.ext, Alistair Francis, 2021/10/22
- [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Alistair Francis, 2021/10/22