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[PATCH v4 14/17] target/riscv: adding high part of some csrs
From: |
Frédéric Pétrot |
Subject: |
[PATCH v4 14/17] target/riscv: adding high part of some csrs |
Date: |
Mon, 25 Oct 2021 14:28:15 +0200 |
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 4 ++++
target/riscv/machine.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 923ef01583..d8093be74d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -194,6 +194,10 @@ struct CPURISCVState {
target_ulong hgatp;
uint64_t htimedelta;
+ /* Upper 64-bits of 128-bit CSRs */
+ uint64_t mscratchh;
+ uint64_t sscratchh;
+
/* Virtual CSRs */
/*
* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 78636ec96d..df4e667c59 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -153,6 +153,8 @@ static const VMStateDescription vmstate_rv128 = {
.needed = rv128_needed,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
+ VMSTATE_UINT64(env.mscratchh, RISCVCPU),
+ VMSTATE_UINT64(env.sscratchh, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
--
2.33.0
- Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, (continued)
- [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/25
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
- [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 14/17] target/riscv: adding high part of some csrs,
Frédéric Pétrot <=
- [PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/25
- [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 13/17] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/25