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Re: [PATCH v4 07/17] target/riscv: moving some insns close to similar in
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v4 07/17] target/riscv: moving some insns close to similar insns |
Date: |
Mon, 25 Oct 2021 17:56:32 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 |
On 10/25/21 14:28, Frédéric Pétrot wrote:
> lwu and ld are functionally close to the other loads, but were after the
> stores in the source file.
> Similarly, xor was away from or and and by two arithmetic functions, while
> the immediate versions were nicely put together.
> This patch moves the aforementioned loads after lhu, and xor above or,
> where they more logically belong.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
> 1 file changed, 17 insertions(+), 17 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
- [PATCH v4 00/17] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/25
- [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/25
- Re: [PATCH v4 07/17] target/riscv: moving some insns close to similar insns,
Philippe Mathieu-Daudé <=
- [PATCH v4 03/17] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/25
- [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, Frédéric Pétrot, 2021/10/25
- [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/25
- [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/25