+ /* User Pointer Masking */
+ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte
},
+ [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask,
write_upmmask },
+ [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,
write_upmbase },
+ /* Machine Pointer Masking */
+ [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte
},
+ [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask,
write_mpmmask },
+ [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase,
write_mpmbase },
+ /* Supervisor Pointer Masking */
+ [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte
},
+ [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask,
write_spmmask },
+ [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,
write_spmbase },