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[PULL v2 03/18] hw/riscv: sifive_u: Use the PLIC config helper function
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From: |
Alistair Francis |
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Subject: |
[PULL v2 03/18] hw/riscv: sifive_u: Use the PLIC config helper function |
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Date: |
Fri, 29 Oct 2021 17:08:02 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com
---
include/hw/riscv/sifive_u.h | 1 -
hw/riscv/sifive_u.c | 14 +-------------
2 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index f71c90c94c..8f63a183c4 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -156,7 +156,6 @@ enum {
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
#define SIFIVE_U_COMPUTE_CPU_COUNT 4
-#define SIFIVE_U_PLIC_HART_CONFIG "MS"
#define SIFIVE_U_PLIC_NUM_SOURCES 54
#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0217006c27..589ae72a59 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -811,7 +811,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
**errp)
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
char *plic_hart_config;
- size_t plic_hart_config_len;
int i, j;
NICInfo *nd = &nd_table[0];
@@ -852,18 +851,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error
**errp)
l2lim_mem);
/* create PLIC hart topology configuration string */
- plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
- ms->smp.cpus;
- plic_hart_config = g_malloc0(plic_hart_config_len);
- for (i = 0; i < ms->smp.cpus; i++) {
- if (i != 0) {
- strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
- plic_hart_config_len);
- } else {
- strncat(plic_hart_config, "M", plic_hart_config_len);
- }
- plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
- }
+ plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
/* MMIO */
s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
--
2.31.1
- [PULL v2 00/18] riscv-to-apply queue, Alistair Francis, 2021/10/29
- [PULL v2 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration, Alistair Francis, 2021/10/29
- [PULL v2 02/18] hw/riscv: boot: Add a PLIC config string function, Alistair Francis, 2021/10/29
- [PULL v2 03/18] hw/riscv: sifive_u: Use the PLIC config helper function,
Alistair Francis <=
- [PULL v2 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function, Alistair Francis, 2021/10/29
- [PULL v2 05/18] hw/riscv: virt: Use the PLIC config helper function, Alistair Francis, 2021/10/29
- [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/29
- [PULL v2 07/18] target/riscv: Add J-extension into RISC-V, Alistair Francis, 2021/10/29
- [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/29
- [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/29
- [PULL v2 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/29
- [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/29
- [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alistair Francis, 2021/10/29
- [PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/29