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[PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instructi
From: |
frank . chang |
Subject: |
[PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instruction |
Date: |
Fri, 29 Oct 2021 16:59:03 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.c.inc | 23 -----------------------
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 82484fda751..20b3095f56c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -632,7 +632,6 @@ viota_m 010100 . ..... 10000 010 ..... 1010111
@r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
-vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 4c5f813ccf9..1ce5a10b6a8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2840,8 +2840,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
*** Vector Permutation Instructions
*/
-/* Integer Extract Instruction */
-
static void load_element(TCGv_i64 dest, TCGv_ptr base,
int ofs, int sew, bool sign)
{
@@ -2941,27 +2939,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64
dest,
load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
-static bool trans_vext_x_v(DisasContext *s, arg_r *a)
-{
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv dest = dest_gpr(s, a->rd);
-
- if (a->rs1 == 0) {
- /* Special case vmv.x.s rd, vs2. */
- vec_element_loadi(s, tmp, a->rs2, 0, false);
- } else {
- /* This instruction ignores LMUL and vector register groups */
- int vlmax = s->vlen >> (3 + s->sew);
- vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
- }
-
- tcg_gen_trunc_i64_tl(dest, tmp);
- gen_set_gpr(s, a->rd, dest);
-
- tcg_temp_free_i64(tmp);
- return true;
-}
-
/* Integer Scalar Move Instruction */
static void store_element(TCGv_i64 val, TCGv_ptr base,
--
2.25.1
- [PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions, (continued)
- [PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/10/29
- [PATCH v9 49/76] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/10/29
- [PATCH v9 50/76] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/10/29
- [PATCH v9 52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/10/29
- [PATCH v9 51/76] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/10/29
- [PATCH v9 53/76] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/10/29
- [PATCH v9 54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/10/29
- [PATCH v9 55/76] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/10/29
- [PATCH v9 56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/10/29
- [PATCH v9 57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/10/29
- [PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instruction,
frank . chang <=
- [PATCH v9 59/76] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/10/29
- [PATCH v9 60/76] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/10/29
- [PATCH v9 61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/10/29
- [PATCH v9 62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/10/29
- [PATCH v9 63/76] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/10/29
- [PATCH v9 64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/10/29
- [PATCH v9 65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/10/29
- [PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/10/29
- [PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/10/29
- [PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/10/29