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[PATCH v2 06/34] target/ppc: Implement PLQ and PSTQ
From: |
matheus . ferst |
Subject: |
[PATCH v2 06/34] target/ppc: Implement PLQ and PSTQ |
Date: |
Fri, 29 Oct 2021 17:23:56 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 4 ++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 11e5ea81d6..48756cd4ca 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -38,6 +38,8 @@ PLWA 000001 00 0--.-- .................. \
101001 ..... ..... ................ @PLS_D
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
+PLQ 000001 00 0--.-- .................. \
+ 111000 ..... ..... ................ @PLS_D
### Fixed-Point Store Instructions
@@ -50,6 +52,8 @@ PSTH 000001 10 0--.-- .................. \
PSTD 000001 00 0--.-- .................. \
111101 ..... ..... ................ @PLS_D
+PSTQ 000001 00 0--.-- .................. \
+ 111100 ..... ..... ................ @PLS_D
### Fixed-Point Arithmetic Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index ff35a96459..0d9c6e0996 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -160,6 +160,16 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool
store, bool prefixed)
return true;
}
+static bool do_ldst_quad_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_ldst_quad(ctx, &d, store, true);
+}
+
/* Load Byte and Zero */
TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
@@ -203,6 +213,7 @@ TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
/* Load Quadword */
TRANS64(LQ, do_ldst_quad, false, false);
+TRANS64(PLQ, do_ldst_quad_PLS_D, false);
/* Store Byte */
TRANS(STB, do_ldst_D, false, true, MO_UB)
@@ -234,6 +245,7 @@ TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
/* Store Quadword */
TRANS64(STQ, do_ldst_quad, true, false);
+TRANS64(PSTQ, do_ldst_quad_PLS_D, true);
/*
* Fixed-Point Compare Instructions
--
2.25.1
- [PATCH v2 00/34] PowerISA v3.1 instruction batch, matheus . ferst, 2021/10/29
- [PATCH v2 01/34] target/ppc: introduce do_ea_calc, matheus . ferst, 2021/10/29
- [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree, matheus . ferst, 2021/10/29
- [PATCH v2 05/34] target/ppc: Move LQ and STQ to decodetree, matheus . ferst, 2021/10/29
- [PATCH v2 06/34] target/ppc: Implement PLQ and PSTQ,
matheus . ferst <=
- [PATCH v2 02/34] target/ppc: move resolve_PLS_D to translate.c, matheus . ferst, 2021/10/29
- [PATCH v2 04/34] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions, matheus . ferst, 2021/10/29
- [PATCH v2 07/34] target/ppc: Implement cntlzdm, matheus . ferst, 2021/10/29
- [PATCH v2 08/34] target/ppc: Implement cnttzdm, matheus . ferst, 2021/10/29
- [PATCH v2 09/34] target/ppc: Implement pdepd instruction, matheus . ferst, 2021/10/29
- [PATCH v2 10/34] target/ppc: Implement pextd instruction, matheus . ferst, 2021/10/29
- [PATCH v2 11/34] target/ppc: Move vcfuged to vmx-impl.c.inc, matheus . ferst, 2021/10/29