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[PATCH v2 31/34] target/ppc: Implemented XXSPLTIW using decodetree
From: |
matheus . ferst |
Subject: |
[PATCH v2 31/34] target/ppc: Implemented XXSPLTIW using decodetree |
Date: |
Fri, 29 Oct 2021 17:24:22 -0300 |
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Implemented the XXSPLTIW instruction, using decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn64.decode | 6 ++++++
target/ppc/translate/vsx-impl.c.inc | 10 ++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 134bc60c57..bd71f616cc 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -39,6 +39,10 @@
@8RR_D_IX ...... .. .... .. .. ................ \
...... ..... ... ix:1 . ................ \
&8RR_D_IX si=%8rr_si xt=%8rr_xt
+&8RR_D xt si:int32_t
+@8RR_D ...... .. .... .. .. ................ \
+ ...... ..... .... . ................ \
+ &8RR_D si=%8rr_si xt=%8rr_xt
### Fixed-Point Load Instructions
@@ -165,5 +169,7 @@ PLXVP 000001 00 0--.-- .................. \
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+XXSPLTIW 000001 01 0000 -- -- ................ \
+ 100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 552f05bbda..9b8612ee73 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1466,6 +1466,16 @@ static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8
*a)
return true;
}
+static bool trans_XXSPLTIW(DisasContext *ctx, arg_8RR_D *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_dup_imm(MO_32, vsr_full_offset(a->xt), 16, 16, a->si);
+
+ return true;
+}
+
static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
{
TCGv_i32 imm;
--
2.25.1
- [PATCH v2 23/34] target/ppc: moved stxvx and lxvx from legacy to decodtree, (continued)
- [PATCH v2 23/34] target/ppc: moved stxvx and lxvx from legacy to decodtree, matheus . ferst, 2021/10/29
- [PATCH v2 24/34] target/ppc: added the instructions LXVP and STXVP, matheus . ferst, 2021/10/29
- [PATCH v2 25/34] target/ppc: added the instructions LXVPX and STXVPX, matheus . ferst, 2021/10/29
- [PATCH v2 26/34] target/ppc: added the instructions PLXV and PSTXV, matheus . ferst, 2021/10/29
- [PATCH v2 27/34] target/ppc: added the instructions PLXVP and PSTXVP, matheus . ferst, 2021/10/29
- [PATCH v2 28/34] target/ppc: moved XXSPLTW to using decodetree, matheus . ferst, 2021/10/29
- [PATCH v2 29/34] target/ppc: moved XXSPLTIB to using decodetree, matheus . ferst, 2021/10/29
- [PATCH v2 30/34] target/ppc: implemented XXSPLTI32DX, matheus . ferst, 2021/10/29
- [PATCH v2 31/34] target/ppc: Implemented XXSPLTIW using decodetree,
matheus . ferst <=
- [PATCH v2 32/34] target/ppc: implemented XXSPLTIDP instruction, matheus . ferst, 2021/10/29
- [PATCH v2 33/34] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions, matheus . ferst, 2021/10/29
- [PATCH v2 34/34] target/ppc: Implement lxvkq instruction, matheus . ferst, 2021/10/29
- Re: [PATCH v2 00/34] PowerISA v3.1 instruction batch, David Gibson, 2021/10/31