[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names
From: |
Alistair Francis |
Subject: |
[PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names |
Date: |
Fri, 21 Jan 2022 15:58:06 +1000 |
From: Anup Patel <apatel@ventanamicro.com>
Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 2 --
hw/riscv/spike.c | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 5834c234aa..d937c5c224 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -25,9 +25,7 @@
#include "hw/riscv/riscv_hart.h"
#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
-#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf"
#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
-#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf"
bool riscv_is_32bit(RISCVHartArrayState *harts);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 597df4c288..d059a67f9b 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -260,11 +260,11 @@ static void spike_board_init(MachineState *machine)
*/
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
+ RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
+ RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
}
--
2.31.1
- [PULL 49/61] target/riscv: Create current pm fields in env, (continued)
- [PULL 49/61] target/riscv: Create current pm fields in env, Alistair Francis, 2022/01/21
- [PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base], Alistair Francis, 2022/01/21
- [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, Alistair Francis, 2022/01/21
- [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, Alistair Francis, 2022/01/21
- [PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns, Alistair Francis, 2022/01/21
- [PULL 51/61] target/riscv: Calculate address according to XLEN, Alistair Francis, 2022/01/21
- [PULL 38/61] roms/opensbi: Remove ELF images, Alistair Francis, 2022/01/21
- [PULL 52/61] target/riscv: Split pm_enabled into mask and base, Alistair Francis, 2022/01/21
- [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl, Alistair Francis, 2022/01/21
- [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios, Alistair Francis, 2022/01/21
- [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names,
Alistair Francis <=
- [PULL 40/61] target/riscv: Don't save pc when exception return, Alistair Francis, 2022/01/21
- [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr, Alistair Francis, 2022/01/21
- [PULL 43/61] target/riscv: Create xl field in env, Alistair Francis, 2022/01/21
- [PULL 42/61] target/riscv: Sign extend pc for different XLEN, Alistair Francis, 2022/01/21
- [PULL 44/61] target/riscv: Ignore the pc bits above XLEN, Alistair Francis, 2022/01/21
- [PULL 45/61] target/riscv: Extend pc for runtime pc write, Alistair Francis, 2022/01/21
- [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN, Alistair Francis, 2022/01/21
- [PULL 55/61] target/riscv: Remove VILL field in VTYPE, Alistair Francis, 2022/01/21
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, Alistair Francis, 2022/01/21
- [PULL 46/61] target/riscv: Use gdb xml according to max mxlen, Alistair Francis, 2022/01/21