[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v4 17/42] cxl: Machine level control on whether CXL support i
From: |
Alex Bennée |
Subject: |
Re: [PATCH v4 17/42] cxl: Machine level control on whether CXL support is enabled |
Date: |
Thu, 27 Jan 2022 14:18:02 +0000 |
User-agent: |
mu4e 1.7.6; emacs 28.0.91 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Jonathan Cameron <jonathan.cameron@huawei.com>
>
> There are going to be some potential overheads to CXL enablement,
> for example the host bridge region reserved in memory maps.
> Add a machine level control so that CXL is disabled by default.
>
> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> ---
> hw/arm/virt.c | 1 +
> hw/core/machine.c | 26 ++++++++++++++++++++++++++
> hw/i386/microvm.c | 1 +
> hw/i386/pc.c | 1 +
> hw/ppc/spapr.c | 1 +
> include/hw/boards.h | 2 ++
> include/hw/cxl/cxl.h | 4 ++++
> 7 files changed, 36 insertions(+)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 2b6cc7aa9e..cbb18dcba6 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -2856,6 +2856,7 @@ static void virt_machine_class_init(ObjectClass *oc,
> void *data)
> hc->unplug = virt_machine_device_unplug_cb;
> mc->nvdimm_supported = true;
> mc->smp_props.clusters_supported = true;
> + mc->cxl_supported = false;
You should be able to do this in machine_class_init and then...
<snip>
just turn it on for pc
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index c8696ac01e..b6800a511a 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -1739,6 +1739,7 @@ static void pc_machine_class_init(ObjectClass *oc, void
> *data)
> mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
> mc->nvdimm_supported = true;
> mc->smp_props.dies_supported = true;
> + mc->cxl_supported = true;
> mc->default_ram_id = "pc.ram";
>
<snip>
Otherwise:
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
- Re: [PATCH v4 12/42] hw/pci/cxl: Create a CXL bus type, (continued)
- [PATCH v4 13/42] hw/pxb: Allow creation of a CXL PXB (host bridge), Jonathan Cameron, 2022/01/24
- [PATCH v4 14/42] tests/acpi: allow DSDT.viot table changes., Jonathan Cameron, 2022/01/24
- [PATCH v4 15/42] acpi/pci: Consolidate host bridge setup, Jonathan Cameron, 2022/01/24
- [PATCH v4 16/42] tests/acpi: Add update DSDT.viot, Jonathan Cameron, 2022/01/24
- [PATCH v4 17/42] cxl: Machine level control on whether CXL support is enabled, Jonathan Cameron, 2022/01/24
- Re: [PATCH v4 17/42] cxl: Machine level control on whether CXL support is enabled,
Alex Bennée <=
- [PATCH v4 18/42] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Jonathan Cameron, 2022/01/24
- [PATCH v4 19/42] hw/cxl/rp: Add a root port, Jonathan Cameron, 2022/01/24
- [PATCH v4 20/42] hw/cxl/device: Add a memory device (8.2.8.5), Jonathan Cameron, 2022/01/24
- [PATCH v4 21/42] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Jonathan Cameron, 2022/01/24
- [PATCH v4 22/42] acpi/cxl: Add _OSC implementation (9.14.2), Jonathan Cameron, 2022/01/24
- [PATCH v4 23/42] tests/acpi: allow CEDT table addition, Jonathan Cameron, 2022/01/24
- [PATCH v4 24/42] acpi/cxl: Create the CEDT (9.14.1), Jonathan Cameron, 2022/01/24
- [PATCH v4 25/42] hw/cxl/device: Add some trivial commands, Jonathan Cameron, 2022/01/24
- [PATCH v4 26/42] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Jonathan Cameron, 2022/01/24
- [PATCH v4 27/42] hw/cxl/device: Implement get/set Label Storage Area (LSA), Jonathan Cameron, 2022/01/24