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[PULL 24/32] hw/intc/arm_gicv3_redist: Remove unnecessary zero checks
From: |
Peter Maydell |
Subject: |
[PULL 24/32] hw/intc/arm_gicv3_redist: Remove unnecessary zero checks |
Date: |
Fri, 28 Jan 2022 15:30:01 +0000 |
The ITS-related parts of the redistributor code make some checks for
whether registers like GICR_PROPBASER and GICR_PENDBASER are zero.
There is no requirement in the specification for treating zeroes in
these address registers specially -- they contain guest physical
addresses and it is entirely valid (if unusual) for the guest to
choose to put the tables they address at guest physical address zero.
We use these values only to calculate guest addresses, and attempts
by the guest to use a bad address will be handled by the
address_space_* functions which we use to do the loads and stores.
Remove the unnecessary checks.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-9-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_redist.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 99b11ca5eee..d81d8e5f076 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -591,8 +591,7 @@ void gicv3_redist_update_lpi_only(GICv3CPUState *cs)
idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS),
GICD_TYPER_IDBITS);
- if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser ||
- !cs->gicr_pendbaser) {
+ if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) {
return;
}
@@ -673,9 +672,8 @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq,
int level)
idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS),
GICD_TYPER_IDBITS);
- if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser ||
- !cs->gicr_pendbaser || (irq > (1ULL << (idbits + 1)) - 1) ||
- irq < GICV3_LPI_INTID_START) {
+ if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) ||
+ (irq > (1ULL << (idbits + 1)) - 1) || irq < GICV3_LPI_INTID_START) {
return;
}
--
2.25.1
- [PULL 08/32] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header, (continued)
- [PULL 08/32] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header, Peter Maydell, 2022/01/28
- [PULL 18/32] hw/intc/arm_gicv3_its: Add tracepoints, Peter Maydell, 2022/01/28
- [PULL 22/32] hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs, Peter Maydell, 2022/01/28
- [PULL 19/32] hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS, Peter Maydell, 2022/01/28
- [PULL 32/32] target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp, Peter Maydell, 2022/01/28
- [PULL 30/32] hw/intc/arm_gicv3_its: Implement MOVI, Peter Maydell, 2022/01/28
- [PULL 28/32] hw/intc/arm_gicv3_its: Check table bounds against correct limit, Peter Maydell, 2022/01/28
- [PULL 02/32] hw/armv7m: Fix broken VMStateDescription, Peter Maydell, 2022/01/28
- [PULL 05/32] hw/misc: Add a model of Versal's PMC SLCR, Peter Maydell, 2022/01/28
- [PULL 29/32] hw/intc/arm_gicv3_its: Implement MOVALL, Peter Maydell, 2022/01/28
- [PULL 24/32] hw/intc/arm_gicv3_redist: Remove unnecessary zero checks,
Peter Maydell <=
- [PULL 09/32] hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method, Peter Maydell, 2022/01/28
- [PULL 27/32] hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers, Peter Maydell, 2022/01/28
- [PULL 12/32] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g, Peter Maydell, 2022/01/28
- Re: [PULL 00/32] target-arm queue, Peter Maydell, 2022/01/29