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[PULL 06/19] target/riscv: Fix PMU CSR predicate function
From: |
Alistair Francis |
Subject: |
[PULL 06/19] target/riscv: Fix PMU CSR predicate function |
Date: |
Sun, 3 Jul 2022 10:09:25 +1000 |
From: Atish Patra <atish.patra@wdc.com>
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6dbe9b541f..46bd417cc1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -72,6 +72,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
+ int ctr_index;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
@@ -99,8 +100,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
@@ -126,8 +128,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
- if (!get_field(env->hcounteren, 1 << (csrno -
CSR_HPMCOUNTER3H)) &&
- get_field(env->mcounteren, 1 << (csrno -
CSR_HPMCOUNTER3H))) {
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
--
2.36.1
- [PULL 00/19] riscv-to-apply queue, Alistair Francis, 2022/07/02
- [PULL 02/19] target/riscv: Set env->bins in gen_exception_illegal, Alistair Francis, 2022/07/02
- [PULL 01/19] target/riscv: Remove condition guarding register zero for auipc and lui, Alistair Francis, 2022/07/02
- [PULL 03/19] target/riscv: Remove generate_exception_mtval, Alistair Francis, 2022/07/02
- [PULL 04/19] target/riscv: Minimize the calls to decode_save_opc, Alistair Francis, 2022/07/02
- [PULL 05/19] target/riscv/pmp: guard against PMP ranges with a negative size, Alistair Francis, 2022/07/02
- [PULL 06/19] target/riscv: Fix PMU CSR predicate function,
Alistair Francis <=
- Re: [PULL 00/19] riscv-to-apply queue, Alistair Francis, 2022/07/02