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[PATCH 11/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v6
From: |
Richard Henderson |
Subject: |
[PATCH 11/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v6 |
Date: |
Sun, 3 Jul 2022 13:53:28 +0530 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 5e79c9be98..d70c9120fc 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -532,8 +532,7 @@ do_fault:
static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
- target_ulong *page_size, ARMMMUFaultInfo *fi)
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
int level = 1;
@@ -593,11 +592,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t
address,
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
- *page_size = 0x1000000;
+ result->page_size = 0x1000000;
} else {
/* Section. */
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
- *page_size = 0x100000;
+ result->page_size = 0x100000;
}
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
xn = desc & (1 << 4);
@@ -623,12 +622,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t
address,
case 1: /* 64k page. */
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
xn = desc & (1 << 15);
- *page_size = 0x10000;
+ result->page_size = 0x10000;
break;
case 2: case 3: /* 4k page. */
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
xn = desc & 1;
- *page_size = 0x1000;
+ result->page_size = 0x1000;
break;
default:
/* Never happens, but compiler isn't smart enough to tell. */
@@ -636,7 +635,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t
address,
}
}
if (domain_prot == 3) {
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
} else {
if (pxn && !regime_is_user(env, mmu_idx)) {
xn = 1;
@@ -654,14 +653,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t
address,
fi->type = ARMFault_AccessFlag;
goto do_fault;
}
- *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
+ result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
} else {
- *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
+ result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
}
- if (*prot && !xn) {
- *prot |= PAGE_EXEC;
+ if (result->prot && !xn) {
+ result->prot |= PAGE_EXEC;
}
- if (!(*prot & (1 << access_type))) {
+ if (!(result->prot & (1 << access_type))) {
/* Access permission fault. */
fi->type = ARMFault_Permission;
goto do_fault;
@@ -672,9 +671,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t
address,
* the CPU doesn't support TZ or this is a non-secure translation
* regime, because the attribute will already be non-secure.
*/
- attrs->secure = false;
+ result->attrs.secure = false;
}
- *phys_ptr = phys_addr;
+ result->phys = phys_addr;
return false;
do_fault:
fi->domain = domain;
@@ -2512,8 +2511,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
result, fi);
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, address, access_type, mmu_idx,
- &result->phys, &result->attrs,
- &result->prot, &result->page_size, fi);
+ result, fi);
} else {
return get_phys_addr_v5(env, address, access_type, mmu_idx,
&result->phys, &result->prot,
--
2.34.1
- Re: [PATCH 04/62] target/arm: Record tagged bit for user-only in sve_probe_page, (continued)
- [PATCH 05/62] target/arm: Use PageEntryExtra for MTE, Richard Henderson, 2022/07/03
- [PATCH 06/62] target/arm: Use PageEntryExtra for BTI, Richard Henderson, 2022/07/03
- [PATCH 07/62] include/exec: Remove target_tlb_bitN from MemTxAttrs, Richard Henderson, 2022/07/03
- [PATCH 09/62] target/arm: Fix ipa_secure in get_phys_addr, Richard Henderson, 2022/07/03
- [PATCH 08/62] target/arm: Create GetPhysAddrResult, Richard Henderson, 2022/07/03
- [PATCH 10/62] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 11/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v6,
Richard Henderson <=
- [PATCH 12/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v5, Richard Henderson, 2022/07/03
- [PATCH 13/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5, Richard Henderson, 2022/07/03
- [PATCH 14/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7, Richard Henderson, 2022/07/03
- [PATCH 16/62] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup, Richard Henderson, 2022/07/03
- [PATCH 15/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8, Richard Henderson, 2022/07/03
- [PATCH 17/62] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup, Richard Henderson, 2022/07/03
- [PATCH 18/62] target/arm: Add is_secure parameter to v8m_security_lookup, Richard Henderson, 2022/07/03
- [PATCH 19/62] target/arm: Add is_secure parameter to pmsav8_mpu_lookup, Richard Henderson, 2022/07/03
- [PATCH 20/62] target/arm: Add is_secure parameter to get_phys_addr_v5, Richard Henderson, 2022/07/03
- [PATCH 21/62] target/arm: Add is_secure parameter to get_phys_addr_v6, Richard Henderson, 2022/07/03