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Re: [PATCH 00/62] target/arm: Implement FEAT_HAFDBS
From: |
Peter Maydell |
Subject: |
Re: [PATCH 00/62] target/arm: Implement FEAT_HAFDBS |
Date: |
Mon, 4 Jul 2022 15:54:06 +0100 |
On Sun, 3 Jul 2022 at 09:25, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This is a major reorg to arm page table walking. While the result
> here is "merely" Hardware-assited Access Flag and Dirty Bit Setting
> (HAFDBS), the ultimate goal is the Realm Management Extension (RME).
> RME "recommends" that HAFDBS be implemented (I_CSLWZ).
>
> For HAFDBS, being able to find a host pointer for the ram that
> backs a given page table entry is required in order to perform the
> atomic update to that PTE. The easiest way to find a host pointer
> is to use the existing softtlb mechanism. Thus all of the page
> table walkers have been adjusted to take an mmu_idx that corresponds
> to the regime in which the page table is stored. In some cases,
> this is a new "physical" mmu_idx that has a permanent 1-1 mapping.
>
> For RME, "physical" addresses also have page permissions, coming
> from the Root realm Granule Protection Table, which can be thought
> of as a third stage page table lookup. So eventually the new
> Secure and Nonsecure physical mmu indexes will joined by
> Realm and Root physical mmu indexes, and all of them will take
> the new Granule Page Table into account.
>
> Previously, we had A-profile allocate separate mmu_idx for secure
> vs non-secure. I've done away with that. Now, I flush all mmu_idx
> when SCR_EL3.NS is changed. I did not see how we could reasonably
> add 8 more mmu_idx for Realm. Moreover, I had a look through ARM
> Trusted Firmware, at the code paths used to change between Secure
> and Nonsecure. We wind up flushing all of these mmu_idx anyway while
> swapping the EL1+EL2 cpregs, so there is no gain at all in attempting
> to keep them live at the same time within qemu.
Is there no SMC/interrupt/etc at all which is handled as a "just do the
thing at EL3" without dropping down to secure EL2/EL1 ?
thanks
-- PMM
- [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult, (continued)
- [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult, Richard Henderson, 2022/07/03
- [PATCH 51/62] target/arm: Add ptw_idx argument to S1_ptw_translate, Richard Henderson, 2022/07/03
- [PATCH 53/62] target/arm: Extract HA and HD in aa64_va_parameters, Richard Henderson, 2022/07/03
- [PATCH 56/62] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Richard Henderson, 2022/07/03
- [PATCH 57/62] target/arm: Add ARMFault_UnsuppAtomicUpdate, Richard Henderson, 2022/07/03
- [PATCH 58/62] target/arm: Remove loop from get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 60/62] target/arm: Don't shift attrs in get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 61/62] target/arm: Consider GP an attribute in get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 62/62] target/arm: Implement FEAT_HAFDBS, Richard Henderson, 2022/07/03
- Re: [PATCH 00/62] target/arm: Implement FEAT_HAFDBS,
Peter Maydell <=