[PATCH] target/i386: Restore TSX features with taa-no

[Zhenzhong Duan]

In L1 kernel side, taa-no is cleared because RTM is disabled
which will lead to below warning when starting L2 qemu:

"warning: host doesn't support requested feature: MSR(10AH).taa-no [bit 8]"

If host isn't susceptible to TSX Async Abort (TAA) vulnerabilities,
exposing TSX to L2 may help performance too.

Fixes: d965dc35592d ("target/i386: Add ARCH_CAPABILITIES related bits into 
Icelake-Server CPU model")
Tested-by: Xiangfei Ma <xiangfeix.ma@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
 target/i386/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6a57ef13af86..bda2569c73cc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3423,6 +3423,9 @@ static const X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 3,
                 .props = (PropValue[]) {
+                    /* Restore TSX features removed by -v2 above */
+                    { "hle", "on" },
+                    { "rtm", "on" },
                     { "arch-capabilities", "on" },
                     { "rdctl-no", "on" },
                     { "ibrs-all", "on" },
-- 
2.25.1