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[PULL 02/12] target/mips: implement Octeon-specific BBIT instructions
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PULL 02/12] target/mips: implement Octeon-specific BBIT instructions |
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Date: |
Tue, 12 Jul 2022 22:53:37 +0200 |
From: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
This patch introduces Octeon-specific decoder and implements
check-bit-and-jump instructions.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165572672705.167724.16667636081912075906.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/octeon.decode | 9 +++++++++
target/mips/tcg/octeon_translate.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index b21c735a6c..8062715578 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -4,3 +4,12 @@
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
+
+# Branch on bit set or clear
+# BBIT0 110010 ..... ..... ................
+# BBIT032 110110 ..... ..... ................
+# BBIT1 111010 ..... ..... ................
+# BBIT132 111110 ..... ..... ................
+
+%bbit_p 28:1 16:5
+BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
diff --git a/target/mips/tcg/octeon_translate.c
b/target/mips/tcg/octeon_translate.c
index 8b5eb1a823..1558f74a8e 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -14,3 +14,33 @@
/* Include the auto-generated decoder. */
#include "decode-octeon.c.inc"
+
+static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
+{
+ TCGv p;
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
+ TARGET_FMT_lx "\n", ctx->base.pc_next);
+ generate_exception_end(ctx, EXCP_RI);
+ return true;
+ }
+
+ /* Load needed operands */
+ TCGv t0 = tcg_temp_new();
+ gen_load_gpr(t0, a->rs);
+
+ p = tcg_constant_tl(1ULL << a->p);
+ if (a->set) {
+ tcg_gen_and_tl(bcond, p, t0);
+ } else {
+ tcg_gen_andc_tl(bcond, p, t0);
+ }
+
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ tcg_temp_free(t0);
+ return true;
+}
--
2.36.1
- [PULL 00/12] MIPS patches for 2022-07-12, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 01/12] target/mips: introduce decodetree structure for Cavium Octeon extension, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 02/12] target/mips: implement Octeon-specific BBIT instructions,
Philippe Mathieu-Daudé <=
- [PULL 03/12] target/mips: implement Octeon-specific arithmetic instructions, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 05/12] target/mips: Create report_fault for semihosting, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 04/12] target/mips: introduce Cavium Octeon CPU model, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 06/12] target/mips: Drop link syscall from semihosting, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 07/12] target/mips: Use semihosting/syscalls.h, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 08/12] target/mips: Avoid qemu_semihosting_log_out for UHI_plog, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 09/12] target/mips: Use error_report for UHI_assert, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 10/12] semihosting: Remove qemu_semihosting_log_out, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 11/12] target/mips: Simplify UHI_argnlen and UHI_argn, Philippe Mathieu-Daudé, 2022/07/12
- [PULL 12/12] target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRING, Philippe Mathieu-Daudé, 2022/07/12