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[PATCH v9 09/11] i386/pc: bounds check phys-bits against max used GPA
From: |
Joao Martins |
Subject: |
[PATCH v9 09/11] i386/pc: bounds check phys-bits against max used GPA |
Date: |
Tue, 19 Jul 2022 18:00:12 +0100 |
Calculate max *used* GPA against the CPU maximum possible address
and error out if the former surprasses the latter. This ensures
max used GPA is reacheable by configured phys-bits. Default phys-bits
on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough for the CPU to
address 1Tb (0xff ffff ffff) or 1010G (0xfc ffff ffff) in AMD hosts
with IOMMU.
This is preparation for AMD guests with >1010G, where it will want relocate
ram-above-4g to be after 1Tb instead of 4G.
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
---
hw/i386/pc.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 4ebc45773c29..1e7bd549bfe9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -879,6 +879,18 @@ static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
return start;
}
+static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
+{
+ X86CPU *cpu = X86_CPU(first_cpu);
+
+ /* 32-bit systems don't have hole64 thus return max CPU address */
+ if (cpu->phys_bits <= 32) {
+ return ((hwaddr)1 << cpu->phys_bits) - 1;
+ }
+
+ return pc_pci_hole64_start() + pci_hole64_size - 1;
+}
+
void pc_memory_init(PCMachineState *pcms,
MemoryRegion *system_memory,
MemoryRegion *rom_memory,
@@ -893,13 +905,28 @@ void pc_memory_init(PCMachineState *pcms,
MachineClass *mc = MACHINE_GET_CLASS(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
X86MachineState *x86ms = X86_MACHINE(pcms);
+ hwaddr maxphysaddr, maxusedaddr;
hwaddr cxl_base, cxl_resv_end = 0;
+ X86CPU *cpu = X86_CPU(first_cpu);
assert(machine->ram_size == x86ms->below_4g_mem_size +
x86ms->above_4g_mem_size);
linux_boot = (machine->kernel_filename != NULL);
+ /*
+ * phys-bits is required to be appropriately configured
+ * to make sure max used GPA is reachable.
+ */
+ maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
+ maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
+ if (maxphysaddr < maxusedaddr) {
+ error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
+ " phys-bits too low (%u)",
+ maxphysaddr, maxusedaddr, cpu->phys_bits);
+ exit(EXIT_FAILURE);
+ }
+
/*
* Split single memory region and use aliases to address portions of it,
* done for backwards compatibility with older qemus.
--
2.17.2
- [PATCH v9 00/11] i386/pc: Fix creation of >= 1010G guests on AMD systems with IOMMU, Joao Martins, 2022/07/19
- [PATCH v9 02/11] i386/pc: create pci-host qdev prior to pc_memory_init(), Joao Martins, 2022/07/19
- [PATCH v9 04/11] i386/pc: factor out above-4g end to an helper, Joao Martins, 2022/07/19
- [PATCH v9 01/11] hw/i386: add 4g boundary start to X86MachineState, Joao Martins, 2022/07/19
- [PATCH v9 05/11] i386/pc: factor out cxl range end to helper, Joao Martins, 2022/07/19
- [PATCH v9 06/11] i386/pc: factor out cxl range start to helper, Joao Martins, 2022/07/19
- [PATCH v9 09/11] i386/pc: bounds check phys-bits against max used GPA,
Joao Martins <=
- [PATCH v9 11/11] i386/pc: restrict AMD only enforcing of 1Tb hole to new machine type, Joao Martins, 2022/07/19
- [PATCH v9 03/11] i386/pc: pass pci_hole64_size to pc_memory_init(), Joao Martins, 2022/07/19
- [PATCH v9 07/11] i386/pc: handle unitialized mr in pc_get_cxl_range_end(), Joao Martins, 2022/07/19
- [PATCH v9 08/11] i386/pc: factor out device_memory base/size to helper, Joao Martins, 2022/07/19
- [PATCH v9 10/11] i386/pc: relocate 4g start to 1T where applicable, Joao Martins, 2022/07/19