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Re: [PATCH v4 0/7] tcg: pc-relative translation blocks


From: Richard Henderson
Subject: Re: [PATCH v4 0/7] tcg: pc-relative translation blocks
Date: Tue, 6 Sep 2022 10:29:24 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0

On 9/6/22 10:28, Richard Henderson wrote:
On 9/6/22 10:11, Richard Henderson wrote:
The goal here is to reduce the amount of code generation when the
guest kernel enables address space randomization.  This requires
extensive changes to each target, so opt-in with TARGET_TB_PCREL.

This is split out of v3, which also contained target/arm changes,
as I now have patches for x86 and s390x as well.


r~


Based-on: 20220905202259.189852-1-richard.henderson@linaro.org
("[PATCH v3 0/6] tcg: Introduce CPUTLBEntryFull")

v2: https://lore.kernel.org/qemu-devel/20220816203400.161187-1-richard.henderson@linaro.org/ v3: https://lore.kernel.org/qemu-devel/20220822232338.1727934-1-richard.henderson@linaro.org/

branch: https://gitlab.com/rth7680/qemu/-/tree/tcg-pcrel

Arg.  Accidentally dropped a patch from v3:

... and managed to hit ctrl-enter while pasting ...

https://lore.kernel.org/qemu-devel/20220822232338.1727934-2-richard.henderson@linaro.org/


r~



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