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[PATCH v2 6/8] target/ppc: Set OV32 when OV is set
From: |
Víctor Colombo |
Subject: |
[PATCH v2 6/8] target/ppc: Set OV32 when OV is set |
Date: |
Tue, 6 Sep 2022 09:55:21 -0300 |
According to PowerISA: "OV32 is set whenever OV is implicitly set, and
is set to the same value that OV is defined to be set to in 32-bit
mode".
This patch changes helper_update_ov_legacy to set/clear ov32 when
applicable.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/int_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index d905f07d02..696096100b 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -37,9 +37,9 @@
static inline void helper_update_ov_legacy(CPUPPCState *env, int ov)
{
if (unlikely(ov)) {
- env->so = env->ov = 1;
+ env->so = env->ov = env->ov32 = 1;
} else {
- env->ov = 0;
+ env->ov = env->ov32 = 0;
}
}
--
2.25.1
- [PATCH v2 0/8] Multiple ppc instructions fixes, Víctor Colombo, 2022/09/06
- [PATCH v2 1/8] target/ppc: Remove extra space from s128 field in ppc_vsr_t, Víctor Colombo, 2022/09/06
- [PATCH v2 2/8] target/ppc: Remove unused xer_* macros, Víctor Colombo, 2022/09/06
- [PATCH v2 3/8] target/ppc: Zero second doubleword in DFP instructions, Víctor Colombo, 2022/09/06
- [PATCH v2 4/8] target/ppc: Set result to QNaN for DENBCD when VXCVI occurs, Víctor Colombo, 2022/09/06
- [PATCH v2 5/8] target/ppc: Zero second doubleword for VSX madd instructions, Víctor Colombo, 2022/09/06
- [PATCH v2 6/8] target/ppc: Set OV32 when OV is set,
Víctor Colombo <=
- [PATCH v2 7/8] target/ppc: Zero second doubleword of VSR registers for FPR insns, Víctor Colombo, 2022/09/06
- [PATCH v2 8/8] target/ppc: Clear fpstatus flags on helpers missing it, Víctor Colombo, 2022/09/06
- Re: [PATCH v2 0/8] Multiple ppc instructions fixes, Daniel Henrique Barboza, 2022/09/06