[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 25/44] target/riscv: Add Zihintpause support
From: |
Alistair Francis |
Subject: |
[PULL 25/44] target/riscv: Add Zihintpause support |
Date: |
Wed, 7 Sep 2022 10:03:34 +0200 |
From: Dao Lu <daolu@rivosinc.com>
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Dao Lu <daolu@rivosinc.com>
Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++++++-
target/riscv/cpu.c | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++++
4 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 561d7fa92c..4be4b82a83 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -426,6 +426,7 @@ struct RISCVCPUConfig {
bool ext_zkt;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_zihintpause;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4033565393..595fdcdad8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -149,7 +149,12 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
-fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+
+{
+ pause 0000 0001 0000 00000 000 00000 0001111
+ fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+}
+
fence_i ---- ---- ---- ----- 001 ----- 0001111
csrrw ............ ..... 001 ..... 1110011 @csr
csrrs ............ ..... 010 ..... 1110011 @csr
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 966e5f2dd7..d4635c7df4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -73,6 +73,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v),
ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
+ ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0,
ext_zihintpause),
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
@@ -987,6 +988,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index ca8e3d1ea1..c49dbec0eb 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -792,6 +792,22 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a)
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, NULL);
}
+static bool trans_pause(DisasContext *ctx, arg_pause *a)
+{
+ if (!ctx->cfg_ptr->ext_zihintpause) {
+ return false;
+ }
+
+ /*
+ * PAUSE is a no-op in QEMU,
+ * end the TB and return to main loop
+ */
+ gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ return true;
+}
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
--
2.37.2
- [PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions, (continued)
- [PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions, Alistair Francis, 2022/09/07
- [PULL 14/44] docs: List kvm as a supported accelerator on RISC-V, Alistair Francis, 2022/09/07
- [PULL 16/44] target/riscv: rvv: Add mask agnostic for vector load / store instructions, Alistair Francis, 2022/09/07
- [PULL 17/44] target/riscv: rvv: Add mask agnostic for vx instructions, Alistair Francis, 2022/09/07
- [PULL 19/44] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, Alistair Francis, 2022/09/07
- [PULL 18/44] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, Alistair Francis, 2022/09/07
- [PULL 21/44] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, Alistair Francis, 2022/09/07
- [PULL 20/44] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, Alistair Francis, 2022/09/07
- [PULL 22/44] target/riscv: rvv: Add mask agnostic for vector mask instructions, Alistair Francis, 2022/09/07
- [PULL 23/44] target/riscv: rvv: Add mask agnostic for vector permutation instructions, Alistair Francis, 2022/09/07
- [PULL 25/44] target/riscv: Add Zihintpause support,
Alistair Francis <=
- [PULL 24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, Alistair Francis, 2022/09/07
- [PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec(), Alistair Francis, 2022/09/07
- [PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals, Alistair Francis, 2022/09/07
- [PULL 28/44] hw/riscv: opentitan: bump opentitan version, Alistair Francis, 2022/09/07
- [PULL 31/44] hw/riscv: virt: fix uart node name, Alistair Francis, 2022/09/07
- [PULL 35/44] target/riscv: Add xicondops in ISA entry, Alistair Francis, 2022/09/07
- [PULL 43/44] hw/riscv: virt: Add PMU DT node to the device tree, Alistair Francis, 2022/09/07
- [PULL 36/44] target/riscv: Use official extension names for AIA CSRs, Alistair Francis, 2022/09/07
- [PULL 34/44] hw/core: fix platform bus node name, Alistair Francis, 2022/09/07
- [PULL 27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check, Alistair Francis, 2022/09/07