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[PULL 30/44] target/riscv: Remove additional priv version check for mcou
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From: |
Alistair Francis |
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Subject: |
[PULL 30/44] target/riscv: Remove additional priv version check for mcountinhibit |
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Date: |
Wed, 7 Sep 2022 10:03:39 +0200 |
From: Atish Patra <atishp@rivosinc.com>
With .min_priv_version, additiona priv version check is uncessary
for mcountinhibit read/write functions.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220816232321.558250-7-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d81f466c80..4a7078f7d1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1494,10 +1494,6 @@ static RISCVException write_mtvec(CPURISCVState *env,
int csrno,
static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
target_ulong *val)
{
- if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
*val = env->mcountinhibit;
return RISCV_EXCP_NONE;
}
@@ -1508,10 +1504,6 @@ static RISCVException write_mcountinhibit(CPURISCVState
*env, int csrno,
int cidx;
PMUCTRState *counter;
- if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
env->mcountinhibit = val;
/* Check if any other counter is also monitoring cycles/instructions */
--
2.37.2
- [PULL 24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, (continued)
- [PULL 24/44] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior, Alistair Francis, 2022/09/07
- [PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec(), Alistair Francis, 2022/09/07
- [PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals, Alistair Francis, 2022/09/07
- [PULL 28/44] hw/riscv: opentitan: bump opentitan version, Alistair Francis, 2022/09/07
- [PULL 31/44] hw/riscv: virt: fix uart node name, Alistair Francis, 2022/09/07
- [PULL 35/44] target/riscv: Add xicondops in ISA entry, Alistair Francis, 2022/09/07
- [PULL 43/44] hw/riscv: virt: Add PMU DT node to the device tree, Alistair Francis, 2022/09/07
- [PULL 36/44] target/riscv: Use official extension names for AIA CSRs, Alistair Francis, 2022/09/07
- [PULL 34/44] hw/core: fix platform bus node name, Alistair Francis, 2022/09/07
- [PULL 27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check, Alistair Francis, 2022/09/07
- [PULL 30/44] target/riscv: Remove additional priv version check for mcountinhibit,
Alistair Francis <=
- [PULL 32/44] hw/riscv: virt: fix the plic's address cells, Alistair Francis, 2022/09/07
- [PULL 41/44] target/riscv: Simplify counter predicate function, Alistair Francis, 2022/09/07
- [PULL 42/44] target/riscv: Add few cache related PMU events, Alistair Francis, 2022/09/07
- [PULL 37/44] hw/intc: Move mtimer/mtimecmp to aclint, Alistair Francis, 2022/09/07
- [PULL 33/44] hw/riscv: virt: fix syscon subnode paths, Alistair Francis, 2022/09/07
- [PULL 38/44] target/riscv: Add stimecmp support, Alistair Francis, 2022/09/07
- [PULL 39/44] target/riscv: Add vstimecmp support, Alistair Francis, 2022/09/07
- [PULL 40/44] target/riscv: Add sscofpmf extension support, Alistair Francis, 2022/09/07
- [PULL 44/44] target/riscv: Update the privilege field for sscofpmf CSRs, Alistair Francis, 2022/09/07
- Re: [PULL 00/44] riscv-to-apply queue, Stefan Hajnoczi, 2022/09/07