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[PULL 32/44] hw/riscv: virt: fix the plic's address cells
From: |
Alistair Francis |
Subject: |
[PULL 32/44] hw/riscv: virt: fix the plic's address cells |
Date: |
Wed, 7 Sep 2022 10:03:41 +0200 |
From: Conor Dooley <conor.dooley@microchip.com>
When optional AIA PLIC support was added the to the virt machine, the
address cells property was removed leading the issues with dt-validate
on a dump from the virt machine:
/stuff/qemu/qemu.dtb: plic@c000000: '#address-cells' is a required property
From schema:
/stuff/linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Add back the property to suppress the warning.
Reported-by: Rob Herring <robh@kernel.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Message-id: 20220810184612.157317-3-mail@conchuod.ie
Link:
https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Fixes: e6faee6585 ("hw/riscv: virt: Add optional AIA APLIC support to virt
machine")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/virt.h | 1 +
hw/riscv/virt.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 984e55c77f..be4ab8fe7f 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -111,6 +111,7 @@ enum {
#define FDT_PCI_ADDR_CELLS 3
#define FDT_PCI_INT_CELLS 1
+#define FDT_PLIC_ADDR_CELLS 0
#define FDT_PLIC_INT_CELLS 1
#define FDT_APLIC_INT_CELLS 2
#define FDT_IMSIC_INT_CELLS 0
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9d36133b74..f19758e1df 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -466,6 +466,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
qemu_fdt_add_subnode(mc->fdt, plic_name);
qemu_fdt_setprop_cell(mc->fdt, plic_name,
"#interrupt-cells", FDT_PLIC_INT_CELLS);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ "#address-cells", FDT_PLIC_ADDR_CELLS);
qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
(char **)&plic_compat,
ARRAY_SIZE(plic_compat));
--
2.37.2
- [PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec(), (continued)
- [PULL 26/44] hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec(), Alistair Francis, 2022/09/07
- [PULL 29/44] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals, Alistair Francis, 2022/09/07
- [PULL 28/44] hw/riscv: opentitan: bump opentitan version, Alistair Francis, 2022/09/07
- [PULL 31/44] hw/riscv: virt: fix uart node name, Alistair Francis, 2022/09/07
- [PULL 35/44] target/riscv: Add xicondops in ISA entry, Alistair Francis, 2022/09/07
- [PULL 43/44] hw/riscv: virt: Add PMU DT node to the device tree, Alistair Francis, 2022/09/07
- [PULL 36/44] target/riscv: Use official extension names for AIA CSRs, Alistair Francis, 2022/09/07
- [PULL 34/44] hw/core: fix platform bus node name, Alistair Francis, 2022/09/07
- [PULL 27/44] target/riscv: Fix priority of csr related check in riscv_csrrw_check, Alistair Francis, 2022/09/07
- [PULL 30/44] target/riscv: Remove additional priv version check for mcountinhibit, Alistair Francis, 2022/09/07
- [PULL 32/44] hw/riscv: virt: fix the plic's address cells,
Alistair Francis <=
- [PULL 41/44] target/riscv: Simplify counter predicate function, Alistair Francis, 2022/09/07
- [PULL 42/44] target/riscv: Add few cache related PMU events, Alistair Francis, 2022/09/07
- [PULL 37/44] hw/intc: Move mtimer/mtimecmp to aclint, Alistair Francis, 2022/09/07
- [PULL 33/44] hw/riscv: virt: fix syscon subnode paths, Alistair Francis, 2022/09/07
- [PULL 38/44] target/riscv: Add stimecmp support, Alistair Francis, 2022/09/07
- [PULL 39/44] target/riscv: Add vstimecmp support, Alistair Francis, 2022/09/07
- [PULL 40/44] target/riscv: Add sscofpmf extension support, Alistair Francis, 2022/09/07
- [PULL 44/44] target/riscv: Update the privilege field for sscofpmf CSRs, Alistair Francis, 2022/09/07
- Re: [PULL 00/44] riscv-to-apply queue, Stefan Hajnoczi, 2022/09/07
- Re: [PULL 00/44] riscv-to-apply queue, Stefan Hajnoczi, 2022/09/07