Re: [PATCH 2/2] target/riscv: remove fixed numbering from GDB xml feature files

[Alistair Francis]

On Wed, Aug 31, 2022 at 10:45 AM Andrew Burgess <aburgess@redhat.com> wrote:
>
> The fixed register numbering in the various GDB feature files for
> RISC-V only exists because these files were originally copied from the
> GDB source tree.
>
> However, the fixed numbering only exists in the GDB source tree so
> that GDB, when it connects to a target that doesn't provide a target
> description, will use a specific numbering scheme.
>
> That numbering scheme is designed to be compatible with the first
> versions of QEMU (for RISC-V), that didn't send a target description,
> and relied on a fixed numbering scheme.
>
> Because of the way that QEMU manages its target descriptions,
> recording the number of registers in each feature, and just relying on
> GDB's numbering starting from 0, then I propose that we remove all the
> fixed numbering from the RISC-V feature xml files, and just rely on
> the standard numbering scheme.  Plenty of other targets manage their
> xml files this way, e.g. ARM, AArch64, Loongarch, m68k, rx, and s390.
>
> Signed-off-by: Andrew Burgess <aburgess@redhat.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  gdb-xml/riscv-32bit-cpu.xml | 6 +-----
>  gdb-xml/riscv-32bit-fpu.xml | 6 +-----
>  gdb-xml/riscv-64bit-cpu.xml | 6 +-----
>  gdb-xml/riscv-64bit-fpu.xml | 6 +-----
>  4 files changed, 4 insertions(+), 20 deletions(-)
>
> diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
> index 0d07aaec85..466f2c0648 100644
> --- a/gdb-xml/riscv-32bit-cpu.xml
> +++ b/gdb-xml/riscv-32bit-cpu.xml
> @@ -5,13 +5,9 @@
>       are permitted in any medium without royalty provided the copyright
>       notice and this notice are preserved.  -->
>
> -<!-- Register numbers are hard-coded in order to maintain backward
> -     compatibility with older versions of tools that didn't use xml
> -     register descriptions.  -->
> -
>  <!DOCTYPE feature SYSTEM "gdb-target.dtd">
>  <feature name="org.gnu.gdb.riscv.cpu">
> -  <reg name="zero" bitsize="32" type="int" regnum="0"/>
> +  <reg name="zero" bitsize="32" type="int"/>
>    <reg name="ra" bitsize="32" type="code_ptr"/>
>    <reg name="sp" bitsize="32" type="data_ptr"/>
>    <reg name="gp" bitsize="32" type="data_ptr"/>
> diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
> index 84a44ba8df..24aa087031 100644
> --- a/gdb-xml/riscv-32bit-fpu.xml
> +++ b/gdb-xml/riscv-32bit-fpu.xml
> @@ -5,13 +5,9 @@
>       are permitted in any medium without royalty provided the copyright
>       notice and this notice are preserved.  -->
>
> -<!-- Register numbers are hard-coded in order to maintain backward
> -     compatibility with older versions of tools that didn't use xml
> -     register descriptions.  -->
> -
>  <!DOCTYPE feature SYSTEM "gdb-target.dtd">
>  <feature name="org.gnu.gdb.riscv.fpu">
> -  <reg name="ft0" bitsize="32" type="ieee_single" regnum="33"/>
> +  <reg name="ft0" bitsize="32" type="ieee_single"/>
>    <reg name="ft1" bitsize="32" type="ieee_single"/>
>    <reg name="ft2" bitsize="32" type="ieee_single"/>
>    <reg name="ft3" bitsize="32" type="ieee_single"/>
> diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
> index b8aa424ae4..c4d83de09b 100644
> --- a/gdb-xml/riscv-64bit-cpu.xml
> +++ b/gdb-xml/riscv-64bit-cpu.xml
> @@ -5,13 +5,9 @@
>       are permitted in any medium without royalty provided the copyright
>       notice and this notice are preserved.  -->
>
> -<!-- Register numbers are hard-coded in order to maintain backward
> -     compatibility with older versions of tools that didn't use xml
> -     register descriptions.  -->
> -
>  <!DOCTYPE feature SYSTEM "gdb-target.dtd">
>  <feature name="org.gnu.gdb.riscv.cpu">
> -  <reg name="zero" bitsize="64" type="int" regnum="0"/>
> +  <reg name="zero" bitsize="64" type="int"/>
>    <reg name="ra" bitsize="64" type="code_ptr"/>
>    <reg name="sp" bitsize="64" type="data_ptr"/>
>    <reg name="gp" bitsize="64" type="data_ptr"/>
> diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
> index 9856a9d1d3..d0f17f9984 100644
> --- a/gdb-xml/riscv-64bit-fpu.xml
> +++ b/gdb-xml/riscv-64bit-fpu.xml
> @@ -5,10 +5,6 @@
>       are permitted in any medium without royalty provided the copyright
>       notice and this notice are preserved.  -->
>
> -<!-- Register numbers are hard-coded in order to maintain backward
> -     compatibility with older versions of tools that didn't use xml
> -     register descriptions.  -->
> -
>  <!DOCTYPE feature SYSTEM "gdb-target.dtd">
>  <feature name="org.gnu.gdb.riscv.fpu">
>
> @@ -17,7 +13,7 @@
>      <field name="double" type="ieee_double"/>
>    </union>
>
> -  <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>
> +  <reg name="ft0" bitsize="64" type="riscv_double"/>
>    <reg name="ft1" bitsize="64" type="riscv_double"/>
>    <reg name="ft2" bitsize="64" type="riscv_double"/>
>    <reg name="ft3" bitsize="64" type="riscv_double"/>
> --
> 2.25.4
>
>