On Fri, Sep 2, 2022 at 3:24 AM Tyler Ng <tkng@rivosinc.com> wrote:
>
> Updates the register addresses to match the OpenTitan spec.
>
> These changes were made in this commit:
> https://github.com/lowRISC/opentitan/commit/a25e162b8f91bd0ca32258c83d1d480f93327204
Thanks for the patch
We try to keep all OpenTitan devices in sync with each other. QEMU
currently supports OT commit 217a0168ba118503c166a9587819e3811eeb0c0c
We don't want to update a single device without updating all of them.
If you want you are welcome to update all devices to a newer commit
Also, the commits QEMU supports are generally driven by Tock, as
that's the software running on QEMU OT. Have a look here for the board
https://github.com/tock/tock/tree/master/boards/opentitan or here for
the latest update (which QEMU already supports)
https://github.com/tock/tock/pull/3056
Alistair
Alright, thanks for the info. I'll look into it; the AON spec could have changed since that commit as I was using the latest version.
-Tyler
>
> Signed-off-by: Tyler Ng <tkng@rivosinc.com>
> ---
> hw/timer/ibex_timer.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
> index 8c2ca364da..9ffd4821e8 100644
> --- a/hw/timer/ibex_timer.c
> +++ b/hw/timer/ibex_timer.c
> @@ -38,19 +38,19 @@ REG32(ALERT_TEST, 0x00)
> FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
> REG32(CTRL, 0x04)
> FIELD(CTRL, ACTIVE, 0, 1)
> -REG32(CFG0, 0x100)
> - FIELD(CFG0, PRESCALE, 0, 12)
> - FIELD(CFG0, STEP, 16, 8)
> -REG32(LOWER0, 0x104)
> -REG32(UPPER0, 0x108)
> -REG32(COMPARE_LOWER0, 0x10C)
> -REG32(COMPARE_UPPER0, 0x110)
> -REG32(INTR_ENABLE, 0x114)
> +REG32(INTR_ENABLE, 0x100)
> FIELD(INTR_ENABLE, IE_0, 0, 1)
> -REG32(INTR_STATE, 0x118)
> +REG32(INTR_STATE, 0x104)
> FIELD(INTR_STATE, IS_0, 0, 1)
> -REG32(INTR_TEST, 0x11C)
> +REG32(INTR_TEST, 0x108)
> FIELD(INTR_TEST, T_0, 0, 1)
> +REG32(CFG0, 0x10C)
> + FIELD(CFG0, PRESCALE, 0, 12)
> + FIELD(CFG0, STEP, 16, 8)
> +REG32(LOWER0, 0x110)
> +REG32(UPPER0, 0x114)
> +REG32(COMPARE_LOWER0, 0x118)
> +REG32(COMPARE_UPPER0, 0x11C)
>
> static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
> {
> --
> 2.30.2
>