[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive
From: |
Paolo Bonzini |
Subject: |
[PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive |
Date: |
Mon, 12 Sep 2022 01:03:43 +0200 |
The later prefix wins if both are present, make it show in s->prefix too.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9a85010dcd..f8fd93dae0 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -4737,9 +4737,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
switch (b) {
case 0xf3:
prefixes |= PREFIX_REPZ;
+ prefixes &= ~PREFIX_REPNZ;
goto next_byte;
case 0xf2:
prefixes |= PREFIX_REPNZ;
+ prefixes &= ~PREFIX_REPZ;
goto next_byte;
case 0xf0:
prefixes |= PREFIX_LOCK;
--
2.37.2
- [RFC PATCH 00/37] target/i386: new decoder + AVX implementation, Paolo Bonzini, 2022/09/11
- [PATCH 02/37] target/i386: make ldo/sto operations consistent with ldq, Paolo Bonzini, 2022/09/11
- [PATCH 05/37] target/i386: add core of new i386 decoder, Paolo Bonzini, 2022/09/11
- [PATCH 01/37] target/i386: Define XMMReg and access macros, align ZMM registers, Paolo Bonzini, 2022/09/11
- [PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive,
Paolo Bonzini <=
- [PATCH 06/37] target/i386: add ALU load/writeback core, Paolo Bonzini, 2022/09/11
- [PATCH 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext, Paolo Bonzini, 2022/09/11
- [PATCH 08/37] target/i386: add CPUID feature checks to new decoder, Paolo Bonzini, 2022/09/11
- [PATCH 04/37] target/i386: introduce insn_get_addr, Paolo Bonzini, 2022/09/11
- [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes, Paolo Bonzini, 2022/09/11