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[PATCH 04/37] target/i386: introduce insn_get_addr
From: |
Paolo Bonzini |
Subject: |
[PATCH 04/37] target/i386: introduce insn_get_addr |
Date: |
Mon, 12 Sep 2022 01:03:44 +0200 |
The "O" operand type in the Intel SDM needs to load an 8- to 64-bit
unsigned value, while insn_get is limited to 32 bits. Extract the code
out of disas_insn and into a separate function.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 36 ++++++++++++++++++++++++++----------
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index f8fd93dae0..f1aa830fcc 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -2308,6 +2308,31 @@ static void gen_ldst_modrm(CPUX86State *env,
DisasContext *s, int modrm,
}
}
+static inline target_ulong insn_get_addr(CPUX86State *env, DisasContext *s,
MemOp ot)
+{
+ target_ulong ret;
+
+ switch (ot) {
+ case MO_8:
+ ret = x86_ldub_code(env, s);
+ break;
+ case MO_16:
+ ret = x86_lduw_code(env, s);
+ break;
+ case MO_32:
+ ret = x86_ldl_code(env, s);
+ break;
+#ifdef TARGET_X86_64
+ case MO_64:
+ ret = x86_ldq_code(env, s);
+ break;
+#endif
+ default:
+ tcg_abort();
+ }
+ return ret;
+}
+
static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)
{
uint32_t ret;
@@ -5867,16 +5892,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
target_ulong offset_addr;
ot = mo_b_d(b, dflag);
- switch (s->aflag) {
-#ifdef TARGET_X86_64
- case MO_64:
- offset_addr = x86_ldq_code(env, s);
- break;
-#endif
- default:
- offset_addr = insn_get(env, s, s->aflag);
- break;
- }
+ offset_addr = insn_get_addr(env, s, s->aflag);
tcg_gen_movi_tl(s->A0, offset_addr);
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
--
2.37.2
- Re: [PATCH 05/37] target/i386: add core of new i386 decoder, (continued)
- [PATCH 01/37] target/i386: Define XMMReg and access macros, align ZMM registers, Paolo Bonzini, 2022/09/11
- [PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive, Paolo Bonzini, 2022/09/11
- [PATCH 06/37] target/i386: add ALU load/writeback core, Paolo Bonzini, 2022/09/11
- [PATCH 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext, Paolo Bonzini, 2022/09/11
- [PATCH 08/37] target/i386: add CPUID feature checks to new decoder, Paolo Bonzini, 2022/09/11
- [PATCH 04/37] target/i386: introduce insn_get_addr,
Paolo Bonzini <=
- [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes, Paolo Bonzini, 2022/09/11
- [PATCH 09/37] target/i386: add AVX_EN hflag, Paolo Bonzini, 2022/09/11
- [PATCH 12/37] target/i386: add scalar 0F 38 and 0F 3A instruction to new decoder, Paolo Bonzini, 2022/09/11
- [PATCH 13/37] target/i386: remove scalar VEX instructions from old decoder, Paolo Bonzini, 2022/09/11