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Re: [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX
From: |
Paolo Bonzini |
Subject: |
Re: [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX |
Date: |
Thu, 15 Sep 2022 00:45:10 +0200 |
On Tue, Sep 13, 2022 at 12:14 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> > +static void gen_VMOVLPx(DisasContext *s, CPUX86State *env, X86DecodedInsn
> > *decode)
> > +{
> > + int vec_len = sse_vec_len(s, decode);
> > +
> > + tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset +
> > offsetof(XMMReg, XMM_Q(0)));
> > + tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset,
> > vec_len, vec_len);
> > + tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset +
> > offsetof(XMMReg, XMM_Q(0)));
> > +}
>
> You've just been moving i64 pieces in the other functions, why is this one
> different using
> a gvec move in the middle? I do wonder if a generic helper moving
> offset->offset, with
> the comparison wouldn't be helpful within these functions, even when you know
> off1 !=
> off2, due to Q(0) vs Q(1).
Because this one is the only one that has a VEX.256 version (the
operand is type "x"
rather than "dq" as in MOVHLPS, MOVLHPS, MOVHPx).
Paolo
Paolo
- [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX, (continued)
- [PATCH 29/37] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX, Paolo Bonzini, 2022/09/11
- [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, add AVX, Paolo Bonzini, 2022/09/11
- [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX, Paolo Bonzini, 2022/09/11
- Re: [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, add AVX, Richard Henderson, 2022/09/13
[PATCH 32/37] target/i386: implement XSAVE and XRSTOR of AVX registers, Paolo Bonzini, 2022/09/11
[PATCH 33/37] target/i386: Enable AVX cpuid bits when using TCG, Paolo Bonzini, 2022/09/11
[PATCH 36/37] target/i386: move 3DNow completely out of gen_sse, Paolo Bonzini, 2022/09/11
[PATCH 34/37] target/i386: implement VLDMXCSR/VSTMXCSR, Paolo Bonzini, 2022/09/11