On 9/2/22 04:44, Palmer Dabbelt wrote:
-#define TCG_GUEST_DEFAULT_MO 0
+/*
+ * RISC-V has two memory models: TSO is a bit weaker than Intel (MMIO and
+ * fetch), and WMO is approximately equivilant to Arm MCA. Rather than
+ * enforcing orderings on most accesses, just default to the target memory
+ * order.
+ */
+#ifdef TCG_TARGET_SUPPORTS_MCTCG_RVTSO
+# define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+#else
+# define TCG_GUEST_DEFAULT_MO (0)
+#endif
TCG_GUEST_DEFAULT_MO should be allowed to be variable. Since I've not tried
that, it may
not work, but making sure that it does would be the first thing to do.
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -236,6 +236,7 @@ static inline void tb_target_set_jmp_target(uintptr_t
tc_ptr, uintptr_t jmp_rx,
#include "tcg/tcg-mo.h"
#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+#define TCG_TARGET_SUPPORTS_MCTCG_RVTSO 1
Um, no. There's no need for this hackery...
+#ifdef TCG_TARGET_SUPPORTS_MCTCG_RVTSO
+ /*
+ * We only support Ztso on targets that themselves are already TSO, which
+ * means there's no way to provide just RVWMO on those targets. Instead
+ * just default to telling the guest that Ztso is enabled.:
+ */
+ DEFINE_PROP_BOOL("ztso", RISCVCPU, cfg.ext_ztso, true),
+#endif
... you can just as well define the property at runtime, with a runtime check on
TCG_TARGET_DEFAULT_MO.
Though, honestly, I've had patches to add the required barriers sitting around
for the
last few releases, to better support things like x86 on aarch64. I should just
finish
that up.