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Re: [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC proper


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
Date: Sat, 17 Sep 2022 23:03:46 +0200
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.13.0

On 14/9/22 12:11, Alistair Francis via wrote:
On the OpenTitan hardware the resetvec is fixed at the start of ROM. In
QEMU we don't run the ROM code and instead just jump to the next stage.
This means we need to be a little more flexible about what the resetvec
is.

This patch allows us to set the resetvec from the command line with
something like this:
     -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400

This way as the next stage changes we can update the resetvec.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
  include/hw/riscv/opentitan.h | 2 ++
  hw/riscv/opentitan.c         | 8 +++++++-
  2 files changed, 9 insertions(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>



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