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[PULL 13/17] target/ppc: Zero second doubleword of VSR registers for FPR
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 13/17] target/ppc: Zero second doubleword of VSR registers for FPR insns |
Date: |
Tue, 20 Sep 2022 16:41:58 -0300 |
From: Víctor Colombo <victor.colombo@eldorado.org.br>
FPR register are mapped to the first doubleword of the VSR registers.
Since PowerISA v3.1, the second doubleword of the target register
must be zeroed for FP instructions.
This patch does it by writting 0 to the second dw everytime the
first dw is being written using set_fpr.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220906125523.38765-8-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 29939bd923..e810842925 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6443,6 +6443,14 @@ static inline void get_fpr(TCGv_i64 dst, int regno)
static inline void set_fpr(int regno, TCGv_i64 src)
{
tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
+ /*
+ * Before PowerISA v3.1 the result of doubleword 1 of the VSR
+ * corresponding to the target FPR was undefined. However,
+ * most (if not all) real hardware were setting the result to 0.
+ * Starting at ISA v3.1, the result for doubleword 1 is now defined
+ * to be 0.
+ */
+ tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false));
}
static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
--
2.37.3
- [PULL 09/17] target/ppc: Zero second doubleword in DFP instructions, (continued)
- [PULL 09/17] target/ppc: Zero second doubleword in DFP instructions, Daniel Henrique Barboza, 2022/09/20
- [PULL 05/17] target/ppc: Move fsqrts to decodetree, Daniel Henrique Barboza, 2022/09/20
- [PULL 08/17] target/ppc: Remove unused xer_* macros, Daniel Henrique Barboza, 2022/09/20
- [PULL 07/17] target/ppc: Remove extra space from s128 field in ppc_vsr_t, Daniel Henrique Barboza, 2022/09/20
- [PULL 14/17] target/ppc: Clear fpstatus flags on helpers missing it, Daniel Henrique Barboza, 2022/09/20
- [PULL 15/17] hw/ppc: spapr: Use qemu_vfree() to free spapr->htab, Daniel Henrique Barboza, 2022/09/20
- [PULL 12/17] target/ppc: Set OV32 when OV is set, Daniel Henrique Barboza, 2022/09/20
- [PULL 10/17] target/ppc: Set result to QNaN for DENBCD when VXCVI occurs, Daniel Henrique Barboza, 2022/09/20
- [PULL 06/17] target/ppc: Merge fsqrt and fsqrts helpers, Daniel Henrique Barboza, 2022/09/20
- [PULL 17/17] hw/ppc/spapr: Fix code style problems reported by checkpatch, Daniel Henrique Barboza, 2022/09/20
- [PULL 13/17] target/ppc: Zero second doubleword of VSR registers for FPR insns,
Daniel Henrique Barboza <=
- Re: [PULL 00/17] ppc queue, Stefan Hajnoczi, 2022/09/21