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[PULL 2/5] target/m68k: Fix MACSR to CCR
From: |
Laurent Vivier |
Subject: |
[PULL 2/5] target/m68k: Fix MACSR to CCR |
Date: |
Wed, 21 Sep 2022 17:52:08 +0200 |
From: Richard Henderson <richard.henderson@linaro.org>
First, we were writing to the entire SR register, instead
of only the flags portion. Second, we were not clearing C
as per the documentation (X was cleared via the 0xf mask).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220913142818.7802-2-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/translate.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index ffcc761d6011..c9bb05380323 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5912,8 +5912,10 @@ DISAS_INSN(from_mext)
DISAS_INSN(macsr_to_ccr)
{
TCGv tmp = tcg_temp_new();
- tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
- gen_helper_set_sr(cpu_env, tmp);
+
+ /* Note that X and C are always cleared. */
+ tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V);
+ gen_helper_set_ccr(cpu_env, tmp);
tcg_temp_free(tmp);
set_cc_op(s, CC_OP_FLAGS);
}
--
2.37.3
- [PULL 0/5] M68k for 7.2 patches, Laurent Vivier, 2022/09/21
- [PULL 3/5] target/m68k: Perform writback before modifying SR, Laurent Vivier, 2022/09/21
- [PULL 1/5] target/m68k: Implement atomic test-and-set, Laurent Vivier, 2022/09/21
- [PULL 2/5] target/m68k: Fix MACSR to CCR,
Laurent Vivier <=
- [PULL 5/5] target/m68k: always call gen_exit_tb() after writes to SR, Laurent Vivier, 2022/09/21
- [PULL 4/5] target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K, Laurent Vivier, 2022/09/21
- Re: [PULL 0/5] M68k for 7.2 patches, Stefan Hajnoczi, 2022/09/21