Re: [PATCH v2 2/3] hw/intc: sifive_plic.c: Fix interrupt priority index.

[Philippe Mathieu-Daudé]

On 22/9/22 17:58, Tyler Ng wrote:
> Fixes a bug in which the index of the interrupt priority is off by 1.
>
> For example, using an IRQ number of 3 with a priority of 1 is supposed to set
> plic->source_priority[2] = 1, but instead it sets
> plic->source_priority[3] = 1. When an interrupt is claimed to be
> serviced, it checks the index 2 instead of 3.
>
> Found when testing the OpenTitan Always-On watchdog bark interrupt on ZephyrOS.
>
> Fixes: 0feb4a7129eb4f120c75849ddc9e50495c50cb63
>
> Signed-off-by: Tyler Ng <tkng@rivosinc.com>
> ---
>   hw/intc/sifive_plic.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index af4ae3630e..1734e76aef 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -131,7 +131,7 @@ static uint64_t sifive_plic_read(void *opaque,
> hwaddr addr, unsigned size)
>       SiFivePLICState *plic = opaque;
>
>       if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
> -        uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
> +        uint32_t irq = ((addr - plic->priority_base) >> 2) + 0;
>
>           return plic->source_priority[irq];
>       } else if (addr_between(addr, plic->pending_base,
> plic->num_sources >> 3)) {
> @@ -178,7 +178,7 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
>       SiFivePLICState *plic = opaque;
>
>       if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
> -        uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
> +        uint32_t irq = ((addr - plic->priority_base) >> 2) + 0;

Maybe we can remove the ( ... ) + 0;