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[PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{
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From: |
Alistair Francis |
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Subject: |
[PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} |
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Date: |
Fri, 23 Sep 2022 14:06:57 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
- modify check for mcounteren to work in all less-privilege mode
- modify check for scounteren to work only when S mode is enabled
- distinguish the exception type raised by check for scounteren between U
and VU mode
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220817083756.12471-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b96db1b62b..092b425196 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -98,17 +98,22 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
skip_ext_pmu_check:
- if (((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) ||
- ((env->priv == PRV_U) && (!get_field(env->scounteren, ctr_mask)))) {
+ if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
return RISCV_EXCP_ILLEGAL_INST;
}
if (riscv_cpu_virt_enabled(env)) {
- if (!get_field(env->hcounteren, ctr_mask) &&
- get_field(env->mcounteren, ctr_mask)) {
+ if (!get_field(env->hcounteren, ctr_mask) ||
+ (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
}
+
+ if (riscv_has_ext(env, RVS) && env->priv == PRV_U &&
+ !get_field(env->scounteren, ctr_mask)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
#endif
return RISCV_EXCP_NONE;
}
--
2.37.3
- [PULL 00/12] riscv-to-apply queue, Alistair Francis, 2022/09/23
- [PULL 01/12] hw/ssi: ibex_spi: fixup typos in ibex_spi_host, Alistair Francis, 2022/09/23
- [PULL 03/12] docs/system: clean up code escape for riscv virt platform, Alistair Francis, 2022/09/23
- [PULL 04/12] target/riscv: Remove sideleg and sedeleg, Alistair Francis, 2022/09/23
- [PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h},
Alistair Francis <=
- [PULL 02/12] hw/ssi: ibex_spi: update reg addr, Alistair Francis, 2022/09/23
- [PULL 10/12] hw/riscv: opentitan: Expose the resetvec as a SoC property, Alistair Francis, 2022/09/23
- [PULL 07/12] target/riscv: remove fixed numbering from GDB xml feature files, Alistair Francis, 2022/09/23
- [PULL 11/12] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/23
- [PULL 06/12] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, Alistair Francis, 2022/09/23
- [PULL 08/12] target/riscv: Set the CPU resetvec directly, Alistair Francis, 2022/09/23
- [PULL 09/12] hw/riscv: opentitan: Fixup resetvec, Alistair Francis, 2022/09/23
- [PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState, Alistair Francis, 2022/09/23
- Re: [PULL 00/12] riscv-to-apply queue, Stefan Hajnoczi, 2022/09/26