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Re: [PATCH v2 22/37] target/i386: reimplement 0x0f 0x78-0x7f, add AVX
From: |
Paolo Bonzini |
Subject: |
Re: [PATCH v2 22/37] target/i386: reimplement 0x0f 0x78-0x7f, add AVX |
Date: |
Mon, 26 Sep 2022 09:24:39 +0200 |
On Sat, Sep 24, 2022 at 10:43 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
> > +static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry
> > *entry, uint8_t *b)
> > +{
> > + if (s->prefix & PREFIX_REPNZ) {
> > + entry->gen = gen_INSERTQ_r;
> > + } else if (s->prefix & PREFIX_DATA) {
> > + entry->gen = gen_EXTRQ_r;
> > + } else {
> > + entry->gen = NULL;
> > + };
> > +}
> ...
> > + [0x79] = X86_OP_GROUP2(0F79, V,x, U,x, cpuid(SSE4A)),
>
> These are not -- they're AMD New Media.
What's the CPUID bit for these? Neither
https://github.com/intelxed/xed/blob/main/datafiles/amd/xed-amd-sse4a.txt
nor the AMD programmer's manual makes any distinction between
EXTRQ/INSERTQ with register operand and the same instruction with
immediate operands.
Paolo
- [PATCH v2 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext, (continued)
- [PATCH v2 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext, Paolo Bonzini, 2022/09/20
- [PATCH v2 06/37] target/i386: add ALU load/writeback core, Paolo Bonzini, 2022/09/20
- [PATCH v2 25/37] target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes, Paolo Bonzini, 2022/09/20
- [PATCH v2 02/37] target/i386: make ldo/sto operations consistent with ldq, Paolo Bonzini, 2022/09/20
- [PATCH v2 08/37] target/i386: add CPUID feature checks to new decoder, Paolo Bonzini, 2022/09/20
- [PATCH v2 22/37] target/i386: reimplement 0x0f 0x78-0x7f, add AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 19/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 04/37] target/i386: introduce insn_get_addr, Paolo Bonzini, 2022/09/20
- [PATCH v2 03/37] target/i386: REPZ and REPNZ are mutually exclusive, Paolo Bonzini, 2022/09/20
- [PATCH v2 16/37] target/i386: provide 3-operand versions of unary scalar helpers, Paolo Bonzini, 2022/09/20
- [PATCH v2 13/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 12/37] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder, Paolo Bonzini, 2022/09/20
- [PATCH v2 10/37] target/i386: validate VEX prefixes via the instructions' exception classes, Paolo Bonzini, 2022/09/20