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Re: [PATCH v2 24/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7,
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From: |
Paolo Bonzini |
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Subject: |
Re: [PATCH v2 24/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX |
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Date: |
Mon, 26 Sep 2022 09:56:22 +0200 |
On Sat, Sep 24, 2022 at 10:56 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/20/22 17:24, Paolo Bonzini wrote:
> > For LDDQU, using gen_load_sse directly might corrupt the register if
> > the second part of the load fails.
>
> Surely LDDQU is not unique in this? I would think ldo/ldy both need fixing
> to load to
> temps first.
The only other case with an M operand is MOVNTDQA, which is aligned
and therefore in principle should not fail due to a page fault on the
second half. However, it is still possible to have a race so I'll
change it.
Other loads use a W operand, for which the gen_load_sse() is always
performed by the generic code in gen_load(). In that case the
gen_load_sse() is always directed at xmm_t0.
Paolo
- [PATCH v2 15/37] target/i386: support operand merging in binary scalar helpers, (continued)
- [PATCH v2 15/37] target/i386: support operand merging in binary scalar helpers, Paolo Bonzini, 2022/09/20
- [PATCH v2 33/37] target/i386: implement VLDMXCSR/VSTMXCSR, Paolo Bonzini, 2022/09/20
- [PATCH v2 17/37] target/i386: implement additional AVX comparison operators, Paolo Bonzini, 2022/09/20
- [PATCH v2 21/37] target/i386: reimplement 0x0f 0x50-0x5f, add AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 26/37] target/i386: reimplement 0x0f 0x3a, add AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 24/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 36/37] target/i386: move 3DNow to the new decoder, Paolo Bonzini, 2022/09/20
- [PATCH v2 35/37] tests/tcg: extend SSE tests to AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 32/37] target/i386: implement XSAVE and XRSTOR of AVX registers, Paolo Bonzini, 2022/09/20