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Re: [PULL 00/12] riscv-to-apply queue
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From: |
Stefan Hajnoczi |
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Subject: |
Re: [PULL 00/12] riscv-to-apply queue |
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Date: |
Mon, 26 Sep 2022 15:28:52 -0400 |
On Fri, 23 Sept 2022 at 00:08, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2
Hi Alistair,
Please use the HTTPS GitHub repo URL in pull requests. Setting
separate "url" (HTTPS) and "pushUrl" (ssh) settings for your remote in
git-config(1) should solve this problem.
Stefan
- [PULL 04/12] target/riscv: Remove sideleg and sedeleg, (continued)
- [PULL 04/12] target/riscv: Remove sideleg and sedeleg, Alistair Francis, 2022/09/23
- [PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}, Alistair Francis, 2022/09/23
- [PULL 02/12] hw/ssi: ibex_spi: update reg addr, Alistair Francis, 2022/09/23
- [PULL 10/12] hw/riscv: opentitan: Expose the resetvec as a SoC property, Alistair Francis, 2022/09/23
- [PULL 07/12] target/riscv: remove fixed numbering from GDB xml feature files, Alistair Francis, 2022/09/23
- [PULL 11/12] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/23
- [PULL 06/12] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, Alistair Francis, 2022/09/23
- [PULL 08/12] target/riscv: Set the CPU resetvec directly, Alistair Francis, 2022/09/23
- [PULL 09/12] hw/riscv: opentitan: Fixup resetvec, Alistair Francis, 2022/09/23
- [PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState, Alistair Francis, 2022/09/23
- Re: [PULL 00/12] riscv-to-apply queue,
Stefan Hajnoczi <=