Re: [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs

[Alexander Graf]

On 26.09.22 15:38, Alex Bennée wrote:
> We currently have hacks across the hw/ to reference current_cpu to
> work out what the current accessing CPU is. This breaks in some cases
> including using gdbstub to access HW state. As we have MemTxAttrs to
> describe details about the access lets extend it to mention if this is
> a CPU access and which one it is.
>
> There are a number of places we need to fix up including:
>
>    CPU helpers directly calling address_space_*() fns
>    models in hw/ fishing the data out of current_cpu
>    hypervisors offloading device emulation to QEMU
>
> I'll start addressing some of these in following patches.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>
> ---
> v2
>    - use separate field cpu_index
>    - bool for requester_is_cpu
> v3
>    - switch to enum MemTxRequesterType
>    - move helper #define to patch
>    - revert to overloading requester_id
>    - mention hypervisors in commit message
>    - drop cputlb tweaks, they will move to target specific code
> ---
>   include/exec/memattrs.h | 17 ++++++++++++++++-
>   1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
> index 9fb98bc1ef..0fb5f29d25 100644
> --- a/include/exec/memattrs.h
> +++ b/include/exec/memattrs.h
> @@ -14,6 +14,15 @@
>   #ifndef MEMATTRS_H
>   #define MEMATTRS_H
>   
> +/*
> + * Where the memory transaction comes from
> + */
> +typedef enum MemTxRequesterType {
> +    MEMTXATTRS_CPU,
> +    MEMTXATTRS_MSI,


I don't think MSI is any sensible identifier here. What you actually are 
trying to describe are bus messages that may carry additional source 
information - and what you describe as "MSI" here most likely means "no 
further information".

How about you just call it "BUS", "DMA" or literally "UNSPECIFIED" for 
now? Also, why is unspecified not part of the requester type enum?


Alex

> +} MemTxRequesterType;
> +
> +
>   /* Every memory transaction has associated with it a set of
>    * attributes. Some of these are generic (such as the ID of
>    * the bus master); some are specific to a particular kind of
> @@ -43,7 +52,9 @@ typedef struct MemTxAttrs {
>        * (see MEMTX_ACCESS_ERROR).
>        */
>       unsigned int memory:1;
> -    /* Requester ID (for MSI for example) */
> +    /* Requester type (e.g. CPU or PCI MSI) */
> +    MemTxRequesterType requester_type:2;
> +    /* Requester ID */
>       unsigned int requester_id:16;
>       /* Invert endianness for this page */
>       unsigned int byte_swap:1;
> @@ -66,6 +77,10 @@ typedef struct MemTxAttrs {
>    */
>   #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 })
>   
> +/* Helper for setting a basic CPU sourced transaction */
> +#define MEMTXATTRS_CPU(id) ((MemTxAttrs) \
> +                            {.requester_type = MEMTXATTRS_CPU, .requester_id = 
> id})
> +
>   /* New-style MMIO accessors can indicate that the transaction failed.
>    * A zero (MEMTX_OK) response means success; anything else is a failure
>    * of some kind. The memory subsystem will bitwise-OR together results