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[PULL v2 02/22] hw/ssi: ibex_spi: update reg addr
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From: |
Alistair Francis |
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Subject: |
[PULL v2 02/22] hw/ssi: ibex_spi: update reg addr |
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Date: |
Tue, 27 Sep 2022 16:30:44 +1000 |
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Updates the `EVENT_ENABLE` register to offset `0x34` as per
OpenTitan spec [1].
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220823061201.132342-5-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/ssi/ibex_spi_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index 601041d719..94d7da9cc2 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -93,7 +93,7 @@ REG32(ERROR_STATUS, 0x30)
FIELD(ERROR_STATUS, CMDINVAL, 3, 1)
FIELD(ERROR_STATUS, CSIDINVAL, 4, 1)
FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1)
-REG32(EVENT_ENABLE, 0x30)
+REG32(EVENT_ENABLE, 0x34)
FIELD(EVENT_ENABLE, RXFULL, 0, 1)
FIELD(EVENT_ENABLE, TXEMPTY, 1, 1)
FIELD(EVENT_ENABLE, RXWM, 2, 1)
--
2.37.3
- [PULL v2 00/22] riscv-to-apply queue, Alistair Francis, 2022/09/27
- [PULL v2 01/22] hw/ssi: ibex_spi: fixup typos in ibex_spi_host, Alistair Francis, 2022/09/27
- [PULL v2 02/22] hw/ssi: ibex_spi: update reg addr,
Alistair Francis <=
- [PULL v2 03/22] docs/system: clean up code escape for riscv virt platform, Alistair Francis, 2022/09/27
- [PULL v2 04/22] target/riscv: Remove sideleg and sedeleg, Alistair Francis, 2022/09/27
- [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, Alistair Francis, 2022/09/27
- [PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files, Alistair Francis, 2022/09/27
- [PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec, Alistair Francis, 2022/09/27
- [PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}, Alistair Francis, 2022/09/27
- [PULL v2 08/22] target/riscv: Set the CPU resetvec directly, Alistair Francis, 2022/09/27
- [PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property, Alistair Francis, 2022/09/27
- [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/27
- [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState, Alistair Francis, 2022/09/27