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[PULL v2 03/22] docs/system: clean up code escape for riscv virt platfor
From: |
Alistair Francis |
Subject: |
[PULL v2 03/22] docs/system: clean up code escape for riscv virt platform |
Date: |
Tue, 27 Sep 2022 16:30:45 +1000 |
From: Alex Bennée <alex.bennee@linaro.org>
The example code is rendered slightly mangled due to missing code
block. Properly escape the code block and add shell prompt and qemu to
fit in with the other examples on the page.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index f8ecec95f3..4b16e41d7f 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -168,14 +168,19 @@ Enabling TPM
A TPM device can be connected to the virt board by following the steps below.
-First launch the TPM emulator
+First launch the TPM emulator:
- swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
+.. code-block:: bash
+
+ $ swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unixio,path=swtpm-sock
-Then launch QEMU with:
+Then launch QEMU with some additional arguments to link a TPM device to the
backend:
+
+.. code-block:: bash
- ...
+ $ qemu-system-riscv64 \
+ ... other args .... \
-chardev socket,id=chrtpm,path=swtpm-sock \
-tpmdev emulator,id=tpm0,chardev=chrtpm \
-device tpm-tis-device,tpmdev=tpm0
--
2.37.3
- [PULL v2 00/22] riscv-to-apply queue, Alistair Francis, 2022/09/27
- [PULL v2 01/22] hw/ssi: ibex_spi: fixup typos in ibex_spi_host, Alistair Francis, 2022/09/27
- [PULL v2 02/22] hw/ssi: ibex_spi: update reg addr, Alistair Francis, 2022/09/27
- [PULL v2 03/22] docs/system: clean up code escape for riscv virt platform,
Alistair Francis <=
- [PULL v2 04/22] target/riscv: Remove sideleg and sedeleg, Alistair Francis, 2022/09/27
- [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, Alistair Francis, 2022/09/27
- [PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files, Alistair Francis, 2022/09/27
- [PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec, Alistair Francis, 2022/09/27
- [PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}, Alistair Francis, 2022/09/27
- [PULL v2 08/22] target/riscv: Set the CPU resetvec directly, Alistair Francis, 2022/09/27
- [PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property, Alistair Francis, 2022/09/27
- [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/27
- [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState, Alistair Francis, 2022/09/27
- [PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type, Alistair Francis, 2022/09/27