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[PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigge
From: |
Alistair Francis |
Subject: |
[PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger |
Date: |
Tue, 27 Sep 2022 16:31:01 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Type 2 trigger cannot be fired in VU/VS modes.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220909134215.1843865-8-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 7a8910f980..e16d5c070a 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -464,6 +464,11 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
+ /* type 2 trigger cannot be fired in VU/VS mode */
+ if (riscv_cpu_virt_enabled(env)) {
+ return false;
+ }
+
ctrl = env->tdata1[i];
pc = env->tdata2[i];
@@ -499,6 +504,11 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH:
+ /* type 2 trigger cannot be fired in VU/VS mode */
+ if (riscv_cpu_virt_enabled(env)) {
+ return false;
+ }
+
ctrl = env->tdata1[i];
addr = env->tdata2[i];
flags = 0;
--
2.37.3
- [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, (continued)
- [PULL v2 06/22] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, Alistair Francis, 2022/09/27
- [PULL v2 07/22] target/riscv: remove fixed numbering from GDB xml feature files, Alistair Francis, 2022/09/27
- [PULL v2 09/22] hw/riscv: opentitan: Fixup resetvec, Alistair Francis, 2022/09/27
- [PULL v2 05/22] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}, Alistair Francis, 2022/09/27
- [PULL v2 08/22] target/riscv: Set the CPU resetvec directly, Alistair Francis, 2022/09/27
- [PULL v2 10/22] hw/riscv: opentitan: Expose the resetvec as a SoC property, Alistair Francis, 2022/09/27
- [PULL v2 11/22] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/27
- [PULL v2 12/22] hw/riscv/sifive_e: Fix inheritance of SiFiveEState, Alistair Francis, 2022/09/27
- [PULL v2 13/22] target/riscv: debug: Determine the trigger type from tdata1.type, Alistair Francis, 2022/09/27
- [PULL v2 15/22] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, Alistair Francis, 2022/09/27
- [PULL v2 19/22] target/riscv: debug: Check VU/VS modes for type 2 trigger,
Alistair Francis <=
- [PULL v2 18/22] target/riscv: debug: Create common trigger actions function, Alistair Francis, 2022/09/27
- [PULL v2 16/22] target/riscv: debug: Restrict the range of tselect value can be written, Alistair Francis, 2022/09/27
- [PULL v2 21/22] target/riscv: rvv-1.0: Simplify vfwredsum code, Alistair Francis, 2022/09/27
- [PULL v2 17/22] target/riscv: debug: Introduce tinfo CSR, Alistair Francis, 2022/09/27
- [PULL v2 22/22] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered, Alistair Francis, 2022/09/27
- [PULL v2 14/22] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, Alistair Francis, 2022/09/27
- [PULL v2 20/22] target/riscv: debug: Add initial support of type 6 trigger, Alistair Francis, 2022/09/27
- Re: [PULL v2 00/22] riscv-to-apply queue, Stefan Hajnoczi, 2022/09/27