[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH] mem/cxl-type3: Add sn option to provide serial number for PC
From: |
Ben Widawsky |
Subject: |
Re: [PATCH] mem/cxl-type3: Add sn option to provide serial number for PCI ecap |
Date: |
Tue, 27 Sep 2022 09:45:49 -0700 |
On 22-09-23 17:18:35, Jonathan Cameron wrote:
> The Device Serial Number Extended Capability PCI r6.0 sec 7.9.3
> provides a standard way to provide a device serial number as
> an IEEE defined 64-bit extended unique identifier EUI-64.
>
> CXL 2.0 section 8.1.12.2 Memory Device PCIe Capabilities and
> Extended Capabilities requires this to be used to uniquely
> identify CXL memory devices.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <bwidawsk@kernel.org>
> ---
>
> This is the missing element to be able to use the Linux kernel
> support for PMEM region creation. Without this you can create
> a region, but not remount it after reboot (as the label
> is not valid).
>
> hw/mem/cxl_type3.c | 14 +++++++++++++-
> include/hw/cxl/cxl_device.h | 1 +
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 3bf2869573..e0c1535b73 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -14,6 +14,12 @@
> #include "sysemu/hostmem.h"
> #include "hw/cxl/cxl.h"
>
> +/*
> + * Null value of all Fs suggested by IEEE RA guidelines for use of
> + * EU, OUI and CID
> + */
> +#define UI64_NULL ~(0ULL)
> +
> static void build_dvsecs(CXLType3Dev *ct3d)
> {
> CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
> @@ -149,7 +155,12 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
> pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL);
>
> pcie_endpoint_cap_init(pci_dev, 0x80);
> - cxl_cstate->dvsec_offset = 0x100;
> + if (ct3d->sn != UI64_NULL) {
> + pcie_dev_ser_num_init(pci_dev, 0x100, ct3d->sn);
> + cxl_cstate->dvsec_offset = 0x100 + 0x0c;
> + } else {
> + cxl_cstate->dvsec_offset = 0x100;
> + }
Perhaps just always make it 0x10c to keep it simple and debuggable?
>
> ct3d->cxl_cstate.pdev = pci_dev;
> build_dvsecs(ct3d);
> @@ -275,6 +286,7 @@ static Property ct3_props[] = {
> HostMemoryBackend *),
> DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND,
> HostMemoryBackend *),
> + DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index 1e141b6621..e4d221cdb3 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -237,6 +237,7 @@ struct CXLType3Dev {
> /* Properties */
> HostMemoryBackend *hostmem;
> HostMemoryBackend *lsa;
> + uint64_t sn;
>
> /* State */
> AddressSpace hostmem_as;
> --
> 2.32.0
>