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[PATCH v6 06/18] accel/tcg: Suppress auto-invalidate in probe_access_int
From: |
Richard Henderson |
Subject: |
[PATCH v6 06/18] accel/tcg: Suppress auto-invalidate in probe_access_internal |
Date: |
Fri, 30 Sep 2022 14:26:10 -0700 |
When PAGE_WRITE_INV is set when calling tlb_set_page,
we immediately set TLB_INVALID_MASK in order to force
tlb_fill to be called on the next lookup. Here in
probe_access_internal, we have just called tlb_fill
and eliminated true misses, thus the lookup must be valid.
This allows us to remove a warning comment from s390x.
There doesn't seem to be a reason to change the code though.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 10 +++++++++-
target/s390x/tcg/mem_helper.c | 4 ----
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index d06ff44ce9..264f84a248 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1533,6 +1533,7 @@ static int probe_access_internal(CPUArchState *env,
target_ulong addr,
}
tlb_addr = tlb_read_ofs(entry, elt_ofs);
+ flags = TLB_FLAGS_MASK;
page_addr = addr & TARGET_PAGE_MASK;
if (!tlb_hit_page(tlb_addr, page_addr)) {
if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
@@ -1547,10 +1548,17 @@ static int probe_access_internal(CPUArchState *env,
target_ulong addr,
/* TLB resize via tlb_fill may have moved the entry. */
entry = tlb_entry(env, mmu_idx, addr);
+
+ /*
+ * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
+ * to force the next access through tlb_fill. We've just
+ * called tlb_fill, so we know that this entry *is* valid.
+ */
+ flags &= ~TLB_INVALID_MASK;
}
tlb_addr = tlb_read_ofs(entry, elt_ofs);
}
- flags = tlb_addr & TLB_FLAGS_MASK;
+ flags &= tlb_addr;
/* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index fc52aa128b..3758b9e688 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -148,10 +148,6 @@ static int s390_probe_access(CPUArchState *env,
target_ulong addr, int size,
#else
int flags;
- /*
- * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL
- * to detect if there was an exception during tlb_fill().
- */
env->tlb_fill_exc = 0;
flags = probe_access_flags(env, addr, access_type, mmu_idx, nonfault,
phost,
ra);
--
2.34.1
- [PATCH v6 00/18] tcg: CPUTLBEntryFull and TARGET_TB_PCREL, Richard Henderson, 2022/09/30
- [PATCH v6 01/18] cpu: cache CPUClass in CPUState for hot code paths, Richard Henderson, 2022/09/30
- [PATCH v6 02/18] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs, Richard Henderson, 2022/09/30
- [PATCH v6 03/18] cputlb: used cached CPUClass in our hot-paths, Richard Henderson, 2022/09/30
- [PATCH v6 04/18] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull, Richard Henderson, 2022/09/30
- [PATCH v6 05/18] accel/tcg: Drop addr member from SavedIOTLB, Richard Henderson, 2022/09/30
- [PATCH v6 06/18] accel/tcg: Suppress auto-invalidate in probe_access_internal,
Richard Henderson <=
- [PATCH v6 07/18] accel/tcg: Introduce probe_access_full, Richard Henderson, 2022/09/30
- [PATCH v6 08/18] accel/tcg: Introduce tlb_set_page_full, Richard Henderson, 2022/09/30
- [PATCH v6 09/18] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/09/30
- [PATCH v6 10/18] accel/tcg: Remove PageDesc code_bitmap, Richard Henderson, 2022/09/30
- [PATCH v6 11/18] accel/tcg: Use bool for page_find_alloc, Richard Henderson, 2022/09/30
- [PATCH v6 13/18] accel/tcg: Do not align tb->page_addr[0], Richard Henderson, 2022/09/30
- [PATCH v6 12/18] accel/tcg: Use DisasContextBase in plugin_gen_tb_start, Richard Henderson, 2022/09/30
- [PATCH v6 14/18] accel/tcg: Inline tb_flush_jmp_cache, Richard Henderson, 2022/09/30
- [PATCH v6 15/18] include/hw/core: Create struct CPUJumpCache, Richard Henderson, 2022/09/30
- [PATCH v6 16/18] hw/core: Add CPUClass.get_pc, Richard Henderson, 2022/09/30