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[PULL 05/20] accel/tcg: Drop addr member from SavedIOTLB
From: |
Richard Henderson |
Subject: |
[PULL 05/20] accel/tcg: Drop addr member from SavedIOTLB |
Date: |
Tue, 4 Oct 2022 12:52:26 -0700 |
This field is only written, not read; remove it.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 1 -
accel/tcg/cputlb.c | 7 +++----
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 1a7e1a9380..009dc0d336 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -225,7 +225,6 @@ struct CPUWatchpoint {
* the memory regions get moved around by io_writex.
*/
typedef struct SavedIOTLB {
- hwaddr addr;
MemoryRegionSection *section;
hwaddr mr_offset;
} SavedIOTLB;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index aa22f578cb..d06ff44ce9 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1372,12 +1372,11 @@ static uint64_t io_readx(CPUArchState *env,
CPUTLBEntryFull *full,
* This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
* because of the side effect of io_writex changing memory layout.
*/
-static void save_iotlb_data(CPUState *cs, hwaddr addr,
- MemoryRegionSection *section, hwaddr mr_offset)
+static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section,
+ hwaddr mr_offset)
{
#ifdef CONFIG_PLUGIN
SavedIOTLB *saved = &cs->saved_iotlb;
- saved->addr = addr;
saved->section = section;
saved->mr_offset = mr_offset;
#endif
@@ -1406,7 +1405,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull
*full,
* The memory_region_dispatch may trigger a flush/resize
* so for plugins we save the iotlb_data just in case.
*/
- save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
+ save_iotlb_data(cpu, section, mr_offset);
if (!qemu_mutex_iothread_locked()) {
qemu_mutex_lock_iothread();
--
2.34.1
- [PULL 00/20] tcg patch queue, Richard Henderson, 2022/10/04
- [PULL 05/20] accel/tcg: Drop addr member from SavedIOTLB,
Richard Henderson <=
- [PULL 03/20] cputlb: used cached CPUClass in our hot-paths, Richard Henderson, 2022/10/04
- [PULL 04/20] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull, Richard Henderson, 2022/10/04
- [PULL 07/20] accel/tcg: Introduce probe_access_full, Richard Henderson, 2022/10/04
- [PULL 08/20] accel/tcg: Introduce tlb_set_page_full, Richard Henderson, 2022/10/04
- [PULL 02/20] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs, Richard Henderson, 2022/10/04
- [PULL 06/20] accel/tcg: Suppress auto-invalidate in probe_access_internal, Richard Henderson, 2022/10/04
- [PULL 11/20] accel/tcg: Use bool for page_find_alloc, Richard Henderson, 2022/10/04
- [PULL 01/20] cpu: cache CPUClass in CPUState for hot code paths, Richard Henderson, 2022/10/04
- [PULL 09/20] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA, Richard Henderson, 2022/10/04
- [PULL 10/20] accel/tcg: Remove PageDesc code_bitmap, Richard Henderson, 2022/10/04