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Re: [PULL 19/89] target/riscv: Fix itrigger when icount is used
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From: |
Alistair Francis |
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Subject: |
Re: [PULL 19/89] target/riscv: Fix itrigger when icount is used |
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Date: |
Mon, 8 May 2023 08:22:30 +1000 |
On Fri, May 5, 2023 at 11:04 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> When I boot a ubuntu image, QEMU output a "Bad icount read" message and exit.
> The reason is that when execute helper_mret or helper_sret, it will
> cause a call to icount_get_raw_locked (), which needs set can_do_io flag
> on cpustate.
>
> Thus we setting this flag when execute these two instructions.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This is also a good candidate for 8.0.1
Alistair
> ---
> target/riscv/insn_trans/trans_privileged.c.inc | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
> b/target/riscv/insn_trans/trans_privileged.c.inc
> index 59501b2780..e3bee971c6 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -77,6 +77,9 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
> #ifndef CONFIG_USER_ONLY
> if (has_ext(ctx, RVS)) {
> decode_save_opc(ctx);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_sret(cpu_pc, cpu_env);
> exit_tb(ctx); /* no chaining */
> ctx->base.is_jmp = DISAS_NORETURN;
> @@ -93,6 +96,9 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
> {
> #ifndef CONFIG_USER_ONLY
> decode_save_opc(ctx);
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + }
> gen_helper_mret(cpu_pc, cpu_env);
> exit_tb(ctx); /* no chaining */
> ctx->base.is_jmp = DISAS_NORETURN;
> --
> 2.40.0
>
- [PULL 10/89] target/riscv: add support for Zca extension, (continued)
- [PULL 10/89] target/riscv: add support for Zca extension, Alistair Francis, 2023/05/04
- [PULL 11/89] target/riscv: add support for Zcf extension, Alistair Francis, 2023/05/04
- [PULL 12/89] target/riscv: add support for Zcd extension, Alistair Francis, 2023/05/04
- [PULL 13/89] target/riscv: add support for Zcb extension, Alistair Francis, 2023/05/04
- [PULL 14/89] target/riscv: add support for Zcmp extension, Alistair Francis, 2023/05/04
- [PULL 15/89] target/riscv: add support for Zcmt extension, Alistair Francis, 2023/05/04
- [PULL 16/89] target/riscv: expose properties for Zc* extension, Alistair Francis, 2023/05/04
- [PULL 17/89] disas/riscv.c: add disasm support for Zc*, Alistair Francis, 2023/05/04
- [PULL 18/89] target/riscv: Add support for Zce, Alistair Francis, 2023/05/04
- [PULL 19/89] target/riscv: Fix itrigger when icount is used, Alistair Francis, 2023/05/04
- Re: [PULL 19/89] target/riscv: Fix itrigger when icount is used,
Alistair Francis <=
- [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 21/89] target/riscv: Remove redundant check on RVH, Alistair Francis, 2023/05/04
- [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled, Alistair Francis, 2023/05/04
- [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled, Alistair Francis, 2023/05/04
- [PULL 25/89] target/riscv: Remove redundant parentheses, Alistair Francis, 2023/05/04
- [PULL 26/89] target/riscv: Fix addr type for get_physical_address, Alistair Francis, 2023/05/04
- [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault, Alistair Francis, 2023/05/04
- [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled(), Alistair Francis, 2023/05/04