This makes CPUTLBEntry agnostic to the address size of the guest.
When 32-bit addresses are in effect, we can simply read the low
32 bits of the 64-bit field. Similarly when we need to update
the field for setting TLB_NOTDIRTY.
For TCG backends that could in theory be big-endian, but in
practice are not (arm, loongarch, riscv), use QEMU_BUILD_BUG_ON
to document and ensure this is not accidentally missed.
For s390x, which is always big-endian, use HOST_BIG_ENDIAN anyway,
to document the reason for the adjustment.
For sparc64 and ppc64, always perform a 64-bit load, and rely on
the following 32-bit comparison to ignore the high bits.
Rearrange mips and ppc if ladders for clarity.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-defs.h | 37 +++++++++++---------------------
include/exec/cpu_ldst.h | 19 ++++++++++------
accel/tcg/cputlb.c | 8 +++++--
tcg/aarch64/tcg-target.c.inc | 1 +
tcg/arm/tcg-target.c.inc | 1 +
tcg/loongarch64/tcg-target.c.inc | 1 +
tcg/mips/tcg-target.c.inc | 13 ++++++-----
tcg/ppc/tcg-target.c.inc | 28 +++++++++++++-----------
tcg/riscv/tcg-target.c.inc | 1 +
tcg/s390x/tcg-target.c.inc | 1 +
tcg/sparc64/tcg-target.c.inc | 8 +++++--
11 files changed, 67 insertions(+), 51 deletions(-)